A LOW-POWER SUCCESIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER INTEGRATED CIRCUIT FOR IMAGING SENSORS

Date

2023-3-31

Author

Koçak , Serhat

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This thesis presents a low-power 14-bit successive approximation register analog-to-digital converter (ADC) designed in a CMOS process for the next-generation infrared imaging sensors and readout integrated circuits (ROIC). The ADC consists of 4 main components including input drivers, two digital-to-analog converter (DAC) integrated circuits, a comparator, and a SAR logic, all of which dissipate only 6.3 mW while operating at an 8 MS/s conversion rate. The CMOS integrated circuit has novel architectures in all 4 main components to reduce the power consumption compared to the conventional architectures, while operating at a fast conversion rate for a typical 14-bit successive approximation register ADC. Firstly, the power consumption of the input buffers is decreased by using a charge sharing technique between the two DACs. The charge sharing technique reduces the output voltage swing and provides common-mode voltage at the output of the input buffers without any power consumption at the end of each conversion. As a result, the input buffers achieves 50% reduction in the power consumption. Secondly, each of the capacitive DACs has a split capacitor with 1 bridge capacitor architecture with a novel switching method, which not only decreases the power consumption by 25% compared to the state-of-art methods but also reduces the overall area by 75% compared to the conventional DACs with low common-mode voltage variation. In addition, two more optional novel switching method is proposed to decrease the power consumption further while achieving the same reduction in the overall area. Thirdly, there are two different comparator architecture in this thesis. The coarse comparator has a novel 2-level latch architecture including the pre-driver and strong-arm latch to reduce the power consumption of the strong-arm latch while achieving same noise level compared to the state-of-art comparators. The fine comparator has 2 pre-amplifier followed by a strong-arm latch with dynamic inverters to speed up the conversion cycle. Finally, a modified SAR logic provides less propagation time and minimizes the SAR conversion loop delay compared to the conventional design. A programmable digital controller and a bias generator provide flexible timing and biasing. The proposed novel ADC architecture is designed and implemented in a standard 0.18 µm CMOS process, where it measures 0.5mmx1.3mm, operates from a 2.5V and 1.8 V supply voltage, and dissipates 6.3 mW at 8 MS/s conversion rate without the coarse comparator and 7.2 mW at 8 MS/s with the coarse comparator. The Walden figure of merit (FoM)W is 92.2 fJ/conv-step which is the lowest among all the ADCs with integrated input drivers for 14-bit resolution according to the best of our knowledge.

Subject Keywords

Analog-To-Digital Converter Integrated Circuit, Digital-To-Analog Converter Integrated Circuit, Successive Approximation Register, Low-Power Comparator, Low-Power Input Driver

URI

https://hdl.handle.net/11511/103096

Collections

Graduate School of Natural and Applied Sciences, Thesis