FPGA-FRIENDLY COMPACT AND EFFICIENT AES-LIKE 8X8 S-BOX

Date

2023-6-22

Author

MALAL, Ahmet

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One of the main layers in the Advanced Encryption Standard (AES) is the substitution layer, where an $8 \times 8$ S-Box is used $16$ times. The substitution layer provides confusion and makes the algorithm resistant to cryptanalysis techniques. Therefore, the security of the algorithm is also highly dependent on this layer. However, the cost of implementing $8 \times 8$ S-Box on FPGA platforms is considerably higher than other layers of the algorithm. In 2005, Canright used different extension fields to represent AES S-Box to get FPGA-friendly compact designs. We use the same optimization methods that Canright used to optimize AES S-Box on hardware platforms. Our purpose is not to optimize AES S-Box; we aim to create another an $8 \times 8$ S-Box which is strong and compact enough for FPGA platforms. We create an 8x8 S-Box using the inverse field operation as in the case of AES S-Box. We use another primitive polynomial to represent the finite field and get an FPGA-friendly compact and efficient an $8 \times 8$ S-Box. The finite field we propose provides the same level of security against cryptanalysis techniques with a $3.125\%$ less gate-area on Virtex-7 and Artix-7 FPGAs compared to Canright’s results. Moreover, our proposed S-Box requires $11.76\%$ less gate on Virtex-4 FPGAs. The enhancements made to the gate area offer advantages to IoT devices with limited resources, enabling increased duplication of the S-Box for improved algorithm parallelism. Therefore, we claim that our proposed S-Box is more compact and efficient than AES S-Box.

Subject Keywords

AES, Rijndael S-Box, Compact S-Box, Finite Field, Group Isomorphisms

URI

https://hdl.handle.net/11511/104464

Collections

Graduate School of Informatics, Thesis