CYCLE-ACCURATE FUNCTIONAL SIMULATION OF RISC-V PROCESSORS FOR EMBEDDED APPLICATIONS: TIMING MODEL CONSTRUCTION, VALIDATION AND PERFORMANCE EVALUATION

Download

Utkucan_MSc_Thesis_Final.pdf

Date

2024-8-26

Author

Doğan, Utkucan

Metadata

Show full item record

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Item Usage Stats

295
views

0
downloads

RISC-V is a popular open-source ISA that can be used for real-time embedded applications. It is always under development and thus requires simulators for fast prototyping, verification, performance evaluation, and DSE. Functional simulators perform better than RTL simulators due to speed and ease of use. For these applications, the Imperas ISS and CV32E40P are the ideal choices since the Imperas ISS can be expanded with a timing model, and CV32E40P is designed for embedded real-time use. This thesis proposes a methodology to develop a cycle-accurate timing library for the functional simulator. Our methodology systematically divides each instructions cycle cost into different groups, and it models the base integer instructions, FPU, and a dynamic branch predictor. It implements a CV32E40P timing library for the Imperas ISS simulator using our methodology and a dynamic branch predictor for the core. Our library is verified by comparing the cycle counts obtained from our implementation with Verilator and obtained a more than 99% accuracy, which is better than the literature. Finally, this thesis demonstrates the use case of our timing library by exploring design choices such as FPU parameters and branch predictor algorithms and obtaining results for the best parameter choices for real-time embedded applications. It proposes a design with a combinational FPU, and a branch predictor with 32 entries and two prediction bits for an FPGA implementation.

Subject Keywords

RISC-V, Functional Simulator, Timing Simulator, Cycle-accurate, Real-time, Embedded

URI

https://hdl.handle.net/11511/111275

Collections

Graduate School of Natural and Applied Sciences, Thesis

Citation Formats

U. Doğan, “CYCLE-ACCURATE FUNCTIONAL SIMULATION OF RISC-V PROCESSORS FOR EMBEDDED APPLICATIONS: TIMING MODEL CONSTRUCTION, VALIDATION AND PERFORMANCE EVALUATION,” M.S. - Master of Science, Middle East Technical University, 2024.