32-bit and 64-bit CDC-7-XPUF Implementations on a Zynq-7020 SoC

Date

2025-01-01

Author

Yayla, Oğuz
Yılmaz, Yunus Emre

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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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Physically (or Physical) Unclonable Functions (PUFs) are basic and useful primitives in designing cryptographic systems. PUFs are designed to facilitate device authentication, secure boot, firmware integrity, and secure communications. To achieve these objectives, PUFs must exhibit both consistent repeatability and instance-specific randomness. The Arbiter PUF (APUF), recognized as the first silicon PUF, is capable of generating a substantial number of secret keys instantaneously based on the input, all while maintaining a lightweight design. This advantageous characteristic makes it particularly well-suited for device authentication in applications with constrained resources, especially for Internet-of-Things (IoT) devices. Despite these advantages, APUFs are vulnerable to machine learning (ML) attacks. Hence, those APUF designs were improved to achieve increased resistance against such attacks while maintaining usefulness and efficiency for IoT applications, and Component-Differentially Challenged XOR Arbiters (CDC-XPUFs) were proposed. In this work, ML-resistant 32-bit and 64-bit implementations of the Component-Differentially Challenged XOR Arbiter PUF with 7-stream (CDC-7-XPUF) are carried out. These CDC-7-XPUFs are evaluated using PUF metrics from the literature, and the resource utilization ratios of both implementations are also presented. The implementation setup contains the ZC702 Rev1.1 Evaluation Board, featuring the Xilinx Zynq-7020 SoC, and utilizes a configuration involving three boards for experimental validation.

Subject Keywords

Arbiter PUF, CDC-XPUF, PUF, SoC FPGA

URI

https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105012919415&origin=inward
https://hdl.handle.net/11511/115834

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Graduate School of Applied Mathematics, Conference / Seminar