A HIGH SPEED ANALOG COLUMN READOUT ARCHITECTURE SUPPORTING XGA RESOLUTION UNCOOLED THERMAL IMAGERS

Date

2026-1-22

Author

Yegen, Muhammet Talha

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This thesis presents the design of a high-speed pixel and column structure for CMOS readout integrated circuits (ROICs) designed for large format uncooled resistive microbolometer focal plane arrays (FPAs) for long wavelength infrared (LWIR) thermal imaging. The ROIC subsystems are implemented with a novel column parallel structure that is based on the Constant Current Buffered Direct Injection (CCBDI) topology. The new architecture does not use reference pixels and overcomes the speed and array size limitations of conventional massive parallel readout structures, while enabling a low power consumption per pixel. The designed system supports a 1024 × 768 resolution (Extended Graphics Array, XGA), where pixel pitches can be scaled down to 8µm or below even in a 0.18µm CMOS process node. The ROIC subsystems offer advanced features to achieve a 240 frames per second (FPS) readout capability at the XGA resolution. One of the important features of the circuit is the way of implementing the column to pixel tree multiplexing logic structure that allows fast settling of the signal. The multiplexing logic uses 4 serial MOSFET switches, and the voltage drop on them are reduced with special low switch on resistance structure. One of these MOSFET switches acts a part of multiplexer switch structure when it is off, yet a part of cascoded bias current mirror for pixel resistance bias when it is on, allowing to reduce the pixel components and pitch size. This MOSFET is driven by a single stage inverter based operational amplifier with a 75 dB open loop gain to increase the pixel bias current mirroring accuracy, reducing the error below 30 pA. Further accuracy is obtained by biasing current mirrors with a custom designed reference circuit exhibiting a −34 ppm/◦C temperature coefficient and 55 dB power supply rejection while showing only 0.74% variation under worst case conditions. The new pixel and column architecture is suitable for column based analog-to-digital converters (ADCs). The architecture demonstrates the feasibility of combining high frame rates with low power consumption, while the architecture design is process independent and is adaptable to various CMOS process nodes, as validated by extensive simulations that cover process, voltage, and temperature corners. The system level noise analysis yields a calculated noise equivalent temperature difference (NETD) of 0.5 ◦K at 240 fps operation. The NETD value positions the design for specialized applications such as high-speed combustion engine monitoring and target tracking. The proposed system achieves approximately 40 nW power consumption per pixel which is significantly lower than comparable resistive microbolometer architectures in the literature for a 1024 × 768 focal plane array (FPA) resolution, enabling scalability to a 2048 × 2048 resolution in future systems.

Subject Keywords

Bolometer, High FPS, High Resolution, Column Readout Structure, Scalability

URI

https://hdl.handle.net/11511/118707

Collections

Graduate School of Natural and Applied Sciences, Thesis