High level architecture interface specification

Cengiz, Zeki Savaş


High speed tooltip FRF predictions of arbitrary tool-holder combinations based on operational spindle identification
Postel, M.; Özşahin, Orkun; Altintas, Y. (Elsevier BV, 2018-06-01)
The chatter vibrations in milling are avoided by selecting spindle speeds and depth of cuts from the stability lobes. However, it has been well observed that the structural dynamics of the spindle system change as a function of speed and even feed. As a result, the measurement of spindle structure's Frequency Response Function (FRF) at zero speed does not lead to an accurate prediction of stability lobes, hence the productive cutting conditions cannot be estimated accurately. In this study, an in-process id...
High speed LVDS digital input/output interface circuitries for high resolution imaging sensors /
Soyer, Suhip Tuncer; Akın, Tayfun; Eminoğlu, Selim; Department of Electrical and Electronics Engineering (2015)
In communication systems like WiMAX, WLAN, 3G, 4G and LTE, design of wideband and dual polarized antennas are required. It is known that bandwidth of patch antennas can be broaden by using thick air substrates. The bandwidth can be further improved by using three dimensional feed strucutures that are electromagnetically coupled to the patch. In this thesis, microstrip patch antennas that are excited by elevated wide strips are studied. First, a linearly polarized antenna is considered and the effects of ant...
High speed QWIP FPAs on InP substrates
Eker, S. U.; Arslan, Y.; Beşikci, Cengiz (Elsevier BV, 2011-05-01)
Quantum well infrared photodetector (QWIP) technology has allowed the realization of low cost staring focal plane arrays (FPAs). However, AlGaAs/(In)GaAs QWIP FPAs suffer from low quantum and conversion efficiencies under high frame rate and/or low background conditions.
High speed VLSI implementation of the Rijndael Encryption Algorithm
Sever, Refik; Aşkar, Murat; Department of Electrical and Electronics Engineering (2003)
This thesis study presents a high speed VLSI implementation of the Rijndael Encryption Algorithm, which is selected to be the new Advanced Encryption Standard (AES) Algorithm. Both the encryption and the decryption algorithms of Rijndael are implemented as a single ASIC. Although data size is fixed to 128 bits in the AES, our implementation supports all the data sizes of the original Rijndael Algorithm. The core is optimised for both area and speed. Using 149K gates in a 0.35-æm standard CMOS process, 132 M...
High speed, TMS 32010 based pulse discriminator.
Aydogmuş, Hüseyin Ali; Department of Electrical and Electronics Engineering (1987)
Citation Formats
Z. S. Cengiz, “High level architecture interface specification,” Middle East Technical University, 2002.