A CMOS-compatible high aspect ratio silicon-on-glass in-plane micro-accelerometer

Chae, J
Külah, Haluk
Najafi, K
This paper presents a post-CMOS -compatible micro-machined silicon-on-glass (SOG) in-plane capacitive accelerometer. The accelerometer is a high aspect ratio structure with a 120 mum thick single-crystal silicon proof-mass and 3.4 mum sense gap, bonded to a glass substrate. It is fabricated using a simple 3-mask, 5-step process, and is fully CMOS compatible. A CMOS switched-capacitor readout circuit and an oversampled Sigma-Delta modulator are used to read out capacitance changes from the accelerometer. The CMOS chip is 2.6 x 2.4 mm(2) in size, utilizes chopper stabilization and correlated double sampling techniques, has a 106 dB open-loop dynamic range, a low input offset of 370 muV, and can resolve better than 20 aF. The accelerometer system has a measured sensitivity of 40 mV g(-1) and input referred noise density of 79 mug Hz(-1/2). Using the SOG configuration, a post-CMOS monolithic integration technique is developed. The integration technique utilizes dielectric bridges, silicon islands and the SOG configuration to obtain a simple, robust and post-CMOS-compatible process. Utilizing this technique, an integrated SOG accelerometer has been fabricated using the University of Michigan 3mum CMOS process.

Citation Formats
J. Chae, H. Külah, and K. Najafi, “A CMOS-compatible high aspect ratio silicon-on-glass in-plane micro-accelerometer,” JOURNAL OF MICROMECHANICS AND MICROENGINEERING, vol. 15, no. 2, pp. 336–345, 2005, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/37771.