Memory aspects of finite automata applied to variable length codes.

Aybay, Işık


Memory Polynomial with Shaped Memory Delay Profile and Modeling the Thermal Memory Effect
YÜZER, AHMET HAYRETTİN; Bassam, S. A.; Ghannouchi, F. M.; Demir, Şimşek (2013-12-11)
This paper presents a proposal for a new memory polynomial modeling technique with non-uniform delay taps to capture the thermal memory effects in power amplifiers. In the proposed modeling structure, each order of the memory polynomial is assigned a different memory delay. The delay profile is an exponentially shaped function, instead of equal unit delays for all memory polynomial branches. Three different metrics, the memory effect modeling ratio (MEMR) and the normalized mean square error (NMSE) and spec...
Memory Efficient Factored Abstraction for Reinforcement Learning
Sahin, Coskun; Cilden, Erkin; Polat, Faruk (2015-06-26)
Classical reinforcement learning techniques are often inadequate for problems with large state-space due to curse of dimensionality. If the states can be represented as a set of variables, it is possible to model the environment more compactly. Automatic detection and use of temporal abstractions during learning was proven to be effective to increase learning speed. In this paper, we propose a factored automatic temporal abstraction method based on an existing temporal abstraction strategy, namely extended ...
Memory organization in pipelined hierarchical search structures for packet classification
Rumelili, Çağla Irmak; Bazlamaçcı, Cüneyt Fehmi; Erdem, Oğuzhan; Department of Electrical and Electronics Engineering (2013)
Packet classification is a main requirement in routers to manage network security and traffi c. In high speed networks packet classification in line rates has become a major challenge. Our design mainly benefits from a parallel pipelined architecture implemented on field programmable gate arrays (FPGA) to achieve high speed packet processing. The presented solution is based on Hierarchical Hybrid Search Structure (HHSS) [5]. Our work solves the deep pipeline problem of HHSS in a memory e fficient way. This ...
Power-Delay Analysis of an ABACUS Parallel Integer Multiplier VLSI Implementation
Ercan, Furkan; Muhtaroglu, Ali (2015-03-26)
ABACUS parallel architecture was previously proposed as an alternate integer multiplication approach with column compression and parallel carry futures. This paper presents a VLSI implementation for ABACUS and benchmarks it against the conventional Wallace Tree Multiplier (WTM). Simulations are conducted with UMC180nm technology in Cadence environment. Although WTM implementation results in 26.6% fewer devices, ABACUS implementation has 8.6% less power dissipation with matched delay performance, due to 27.8...
Error Control of MLFMA within a Multiple-Precision Arithmetic Framework
Kalfa, Mert; ERTÜRK, VAKUR BEHÇET; Ergül, Özgür Salih (2018-07-13)
We present a new error control scheme that provides the truncation numbers as well as the required digits of machine precision for the multilevel fast multipole algorithm (MLFMA). The proposed method is valid for all frequencies, whereas the previous studies on error control are valid only for high-frequency problems. When combined with a multiple-precision arithmetic framework, the proposed method can be used to solve low-frequency problems that would otherwise experience overflow issues. Numerical results...
Citation Formats
I. Aybay, “Memory aspects of finite automata applied to variable length codes.,” Middle East Technical University, 1980.