8x8-Bit Multiplier Designed With a New Wave-Pipelining Scheme

Date

2010-06-02

Author

Sever, Refik
Askar, Murat

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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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In this paper, a new wave-pipelining scheme is proposed. In classical wave-pipelining scheme, the data waves propagate on the circuit and the propagating waves are sampled simultaneously when they reach to a synchronization stage. In this new wave-pipelining scheme, only the components of the wave whose delay-difference values reach to a critical value are sampled. Other components, which are not sampled, are aligned with the sampled ones by using active delay elements. This wave-pipelining scheme significantly decreases the number of flip-flops which are used to synchronize the propagating waves. For demonstrating the effectiveness of the new wave-pipelining scheme, an 8x8-bit carry save multiplier is implemented using 0.35 mu m standard CMOS process. Simulation results show that, the multiplier can operate at a speed of 2GHz, by using only 55 flip-flops. Comparing with the mesochronous pipelining scheme, the number of the flip-flops is decreased by 47%.

URI

https://hdl.handle.net/11511/65448

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Department of Electrical and Electronics Engineering, Conference / Seminar

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Citation Formats

R. Sever and M. Askar, “8x8-Bit Multiplier Designed With a New Wave-Pipelining Scheme,” 2010, p. 2095, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/65448.