CUSPARC IP processor: Design, characterization and applications

Date

2010-12-01

Author

Hussein, Ezz El-Din O.
Shams, Shoukry I.
Ali, Mohamed I.
Suleiman, Amr A.Z.
ElWazeer, Khalid
Sobhy, Ehab A.
Ibrahim, Ahmad A.I.
Ibrahim, Ahmed M.G.
Khairy, Mohamed S.
Fouda, Mohamed F.
El-Shafie, Al-Hussein A.
Hareedy, Ahmed
Ahmed, Elsayed A.
Zakaria, Ahmed R.
El-Galaind, Khalid M.
El Sherief, Amr A.
Habib, S.E.-D.

Metadata

Show full item record

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Item Usage Stats

35
views

0
downloads

In this paper, we introduce the design of an IP processor core code-named CUSPARC for Cairo university SPARC processor. This core is a 32 bit pipelined processor that conforms to SPARC v8 ISA. It is complete with 4 register windows, I and D caches, SRAM and flash memory controller, resolution hardware for the data and branch hazards, interrupts and exception handling, instructions to support I/O transfers, and two standard WISHBONE buses to support high speed and low speed IO transfers. The design was downloaded and tested on different FPGA platforms, in addition to 0.35μm and 0.13μm ASIC technologies. CUSPARC has a promising metric of 0.9663 DMIPS/MHz. A novel debugger tool was developed for validating CUSPARC. This tool facilitates the testing of the processor running complex software loads by invoking Mentor's MODELSIM simulator in the background while maintaining a "simulator-like" GUI in the foreground. © 2009 IEEE.

Subject Keywords

CUSPARC, IP processor, Processor design, SPARC

URI

https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=79951690873&origin=inward
https://hdl.handle.net/11511/98443

DOI

https://doi.org/10.1109/icm.2010.5696181

Conference Name

2010 International Conference on Microelectronics, ICM'10

Collections

Department of Electrical and Electronics Engineering, Conference / Seminar

Suggestions

OpenMETU
Core

High performance CMOS capacitive interface circuits for MEMS gyroscopes Silay, Kanber Mithat; Akar, Tayfun; Department of Electrical and Electronics Engineering (2006) This thesis reports the development and analysis of high performance CMOS readout electronics for increasing the performance of MEMS gyroscopes developed at Middle East Technical University (METU). These readout electronics are based on unity gain buffers implemented with source followers. High impedance node biasing problem present in capacitive interfaces is solved with the implementation of a transistor operating in the subthreshold region. A generalized fully differential gyroscope model with force feed...
Broadband Multilevel Fast Multipole Algorithm For Large-Scale Problems With Nonuniform Discretizations Ergül, Özgür Salih; Takrimi, Manouchehr; Erturk, Vakur B. (2016-08-18) We present a broadband implementation of the multilevel fast multipole algorithm (MLFMA) for fast and accurate solutions of multiscale problems involving highly nonuniform discretizations. Incomplete tree structures, which are based on population-based clustering with flexible leaf-level boxes at different levels, are used to handle extremely varying triangulation sizes on the same structures. Superior efficiency and accuracy of the developed implementation, in comparison to the standard and broadband MLFMA...
Direction finding performance of antenna arrays on complex platforms using numerical electromagnetic simulation tools Özeç, Mustafa Onur; Tuncer, Temel Engin; Department of Electrical and Electronics Engineering (2011) An important step for the design of direction finding systems is the performance evaluation using numeric electromagnetic simulation tools. In this thesis, a method is presented for both modeling and simulation in a numeric electromagnetic simulation tool FEKO. The method relies on the data generated by FEKO. The data is then processed by correlative interferometer algorithm. This process is implemented in a MATLAB environment. Different types of antenna arrays including dipole, monopole and discone antenna...
FPGA implementation of neuro-fuzzy system with improved PSO learning KARAKUZU, CİHAN; KARAKAYA, FUAT; Cavuslu, Mehmet Ali (2016-07-01) This paper presents the first hardware implementation of neuro-fuzzy system (NFS) with its metaheuristic learning ability on field programmable gate array (FPGA). Metaheuristic learning of NFS for all of its parameters is accomplished by using the improved particle swarm optimization (iPSO). As a second novelty, a new functional approach, which does not require any memory and multiplier usage, is proposed for the Gaussian membership functions of NFS. NFS and its learning using iPSO are implemented on Xilinx...
Design and FPGA implementation of hash processor Şiltu, Çelebi Tuğba; Aşkar, Murat; Department of Electrical and Electronics Engineering (2007) In this thesis, an FPGA based hash processor is designed and implemented using a hardware description language; VHDL. Hash functions are among the most important cryptographic primitives and used in the several fields of communication integrity and signature authentication. These functions are used to obtain a fixed-size fingerprint or hash value of an arbitrary long message. The hash functions SHA-1 and SHA2-256 are examined in order to find the common instructions to implement them using same hardware blo...

Citation Formats

E. E.-D. O. Hussein et al., “CUSPARC IP processor: Design, characterization and applications,” presented at the 2010 International Conference on Microelectronics, ICM′10, Cairo, Mısır, 2010, Accessed: 00, 2022. [Online]. Available: https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=79951690873&origin=inward.