Ahmed, Ahmed Mamdouh Mohamed
Quantum-Dot Cellular Automata (QCA)-based digital circuit design have several advantages over CMOS, including higher intrinsic switching speeds up to Terahertz, lower power consumption, a smaller circuit footprint, and higher throughput due to the intrinsic signal propagation scheme’s compatibility with pipelining. As a result, QCA is an excellent choice for applications like Artificial Intelligence (AI)-accelerators, where real-time energy efficient performance is required at a low cost. This Thesis investigates a novel QCA design approach based on an optimal mix of Majority and NAND-NOR-INVERTER (NNI) gates with the USE (Universal, Scalable, Efficient) clocking scheme for latency and energy consumption improvements to fundamental building blocks in AI-accelerators, such as multipliers, adders, accumulators, and SRAMs. The proposed approach was used to design the standard 4×4 Vedic multiplier, which resulted in a 62.8% reduction in cell count, 82.2% reduction in area, and 71.2% reduction in latency over state-of-the-art. The proposed 8-bit PIPO register was simulated to have an 83% reduction in cell count, 94.5% reduction in area, and 94.6% reduction in latency. The proposed SRAM cell architecture is expected to achieve comparable performance improvements as the sub-blocks, such as the D-Latch, which has been modeled to achieve a 44.4% reduction in cell count, a 50% reduction in both area and latency, and a 73% reduction in energy dissipation. The results of this research can be directly applied to low-cost, high-throughput, energy efficient AI-accelerators that could potentially deliver orders of magnitude better energy delay characteristics than their CMOS counterparts, and significant improvements over current QCA implementations.


High-performance readout circuit for resonator-based MEMS accelerometer using digital control loop
Ali, Muhammad; Akın, Tayfun; Department of Electrical and Electronics Engineering (2022-11)
This study proposes a new digital control loop-based compact readout circuit for a resonant MEMS accelerometer providing high performance with reduced temperature and power supply dependence while utilizing low processing power. The readout circuit utilizes a charge-sensing pre-amplifier stage that converts the small motional current to readable voltage, which is then converted to the digital domain using a 16-bit ADC to perform the amplitude and frequency extraction in the digital domain. A Proportional In...
Improving the efficiency of microwave power amplifiers without linearity degradation using load and bias tuning in a new configuration
Ronaghzadeh, Amin; Demir, Şimşek; Department of Electrical and Electronics Engineering (2013)
Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power amplifier and...
A Low-power capacitive integrated CMOS readout circuitry for high performance MEMS accelerometers
İncedere, Osman Samet; Akın, Tayfun; Eminoğlu, Selim; Department of Electrical and Electronics Engineering (2013)
This thesis presents a low power capacitive integrated CMOS readout circuitry for high performance MEMS accelerometers. It proposes a linearized model of the complete closed loop accelerometer system, which makes easier of designing and analyzing the system. Designed readout circuitry offers low noise, wide dynamic range and high linearity system with very low power consumption. Designed readout circuit includes proportional integral (PI) controller circuit, which significantly decreases the proof mass defl...
MJEMA, MBONEA GODWIN; Kondo, Satoshi; Yemişcioğlu, Gürtaç; Electrical and Electronics Engineering (2022-8-30)
Over the past two decades, the exponential growth of the number of transis tors in integrated circuits, the so-called Moore’s law, has enabled the design of smaller, faster, and more robust circuits. However, further attempts at size reduction face many challenges due to the physical limits of CMOS; as the gate size reaches below 10nm, the quantum effects are likely to dominate the device’s performance, leading to a reduction in performance and efficiency. Quantum-dot Cellular Automata (QCA) is one of the p...
Linearization of RF power amplifiers with memoryless baseband predistortion method
Kolcuoğlu, Turusan; Demir, Şimşek; Department of Electrical and Electronics Engineering (2011)
In modern wireless communication systems, advanced modulation techniques are used to support more users by handling high data rates and to increase the utilization efficiency of the limited RF spectrum. These techniques are sensitive to the nonlinear distortions due to their high peak to average power ratios. Main source of nonlinear distortion in transmitter topologies are power amplifiers that determine the overall efficiency and linearity of the transmitter. To increase linearity without sacrificing effi...
Citation Formats
A. M. M. Ahmed, “DESIGN OF EFFICIENT AI ACCELERATOR BUILDING BLOCKS IN QUANTUM DOT CELLULAR AUTOMATA (QCA),” M.S. - Master of Science, Middle East Technical University, 2022.