Date

2022-7

Author

Ahmed, Ahmed Mamdouh Mohamed

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Quantum-Dot Cellular Automata (QCA)-based digital circuit design have several advantages over CMOS, including higher intrinsic switching speeds up to Terahertz, lower power consumption, a smaller circuit footprint, and higher throughput due to the intrinsic signal propagation scheme’s compatibility with pipelining. As a result, QCA is an excellent choice for applications like Artificial Intelligence (AI)-accelerators, where real-time energy efficient performance is required at a low cost. This Thesis investigates a novel QCA design approach based on an optimal mix of Majority and NAND-NOR-INVERTER (NNI) gates with the USE (Universal, Scalable, Efficient) clocking scheme for latency and energy consumption improvements to fundamental building blocks in AI-accelerators, such as multipliers, adders, accumulators, and SRAMs. The proposed approach was used to design the standard 4×4 Vedic multiplier, which resulted in a 62.8% reduction in cell count, 82.2% reduction in area, and 71.2% reduction in latency over state-of-the-art. The proposed 8-bit PIPO register was simulated to have an 83% reduction in cell count, 94.5% reduction in area, and 94.6% reduction in latency. The proposed SRAM cell architecture is expected to achieve comparable performance improvements as the sub-blocks, such as the D-Latch, which has been modeled to achieve a 44.4% reduction in cell count, a 50% reduction in both area and latency, and a 73% reduction in energy dissipation. The results of this research can be directly applied to low-cost, high-throughput, energy efficient AI-accelerators that could potentially deliver orders of magnitude better energy delay characteristics than their CMOS counterparts, and significant improvements over current QCA implementations.

Subject Keywords

Quantum cellular automata, Quantum-dots, Nanotechnology, Integrated circuit technology, AI accelerators, SRAM cells

URI

https://hdl.handle.net/11511/99408

Collections

Northern Cyprus Campus, Thesis