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Hardware implementations of neural networks and the Random Neural Network Chip (RNNC)
Date
1998-01-01
Author
Aybay, I
Cerkez, C
Halıcı, Uğur
Badaroglu, M
Metadata
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Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License
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In this study, the basic properties of a number of important Neuro-chips, boards, and computers that have been physically produced shall be presented. Then, a digital MOS chip called RNNC, based on the random neural network model, shall be briefly discussed. The RNNC architecture is cascadable. The synapses of internal neurons within me chip are programmable. The RNNC circuit is implemented using the 0.7 mu m CMOS process.
Subject Keywords
Aritifical Neural Network
,
Neuromorphic Computing
,
Memristor
URI
https://hdl.handle.net/11511/52935
Conference Name
13th International Symposium on Computer and Information Sciences (ISCIS 98)
Collections
Department of Electrical and Electronics Engineering, Conference / Seminar
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I. Aybay, C. Cerkez, U. Halıcı, and M. Badaroglu, “Hardware implementations of neural networks and the Random Neural Network Chip (RNNC),” Antalya, Turkey, 1998, vol. 53, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/52935.