Hardware implementations of neural networks and the Random Neural Network Chip (RNNC)

1998-01-01
Aybay, I
Cerkez, C
Halıcı, Uğur
Badaroglu, M
In this study, the basic properties of a number of important Neuro-chips, boards, and computers that have been physically produced shall be presented. Then, a digital MOS chip called RNNC, based on the random neural network model, shall be briefly discussed. The RNNC architecture is cascadable. The synapses of internal neurons within me chip are programmable. The RNNC circuit is implemented using the 0.7 mu m CMOS process.

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Citation Formats
I. Aybay, C. Cerkez, U. Halıcı, and M. Badaroglu, “Hardware implementations of neural networks and the Random Neural Network Chip (RNNC),” Antalya, Turkey, 1998, vol. 53, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/52935.