A low-power switched-current algorithmic A/D converter

Date

1999-06-02

Author

Tezel, A
Akın, Tayfun

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This paper reports the development of a low-power switched-current algorithmic A/D converter based on a new algorithm, providing the bit conversion in three-cycles. The converter uses modified (SI)-I-2 type current copiers to reduce the overall area and power consumption. The analog portion of the converter occupies only 0.35mm(2) area in 3 mu m CMOS technology. The simulation results show that the converter provides 10 bits resolution with a conversion rate of 61kHz, while dissipating only 1mW power from a single 5V supply.

URI

https://hdl.handle.net/11511/54751

Conference Name

1999 IEEE International Symposium on Circuits and Systems (ISCAS 99)

Collections

Department of Electrical and Electronics Engineering, Conference / Seminar

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Citation Formats

A. Tezel and T. Akın, “A low-power switched-current algorithmic A/D converter,” presented at the 1999 IEEE International Symposium on Circuits and Systems (ISCAS 99), Orlondo, FL, 1999, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/54751.