Low-power and area-efficient finite field arithmetic architecture based on irreducible all-one polynomials

Date

2020-9

Author

Mohaghegh, Shima

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This thesis presents a low-power and area-efficient finite field multiplier based on irreducible all-one polynomials (AOP). The proposed organization implements the AOP multiplication algorithm in three stages, which are reduction network, AND network (multiplication), and three input XOR tree (accumulation), while state-of-the-art implementations distribute reduction, multiplication and accumulation operations in a systolic array. The optimization reduces the overall number of sequential elements and provides lower pipeline latency compared to literature. This leads to the reduction of power dissipation and area for a system clock frequency. Both the previously reported and the proposed architectures have been implemented in Verilog for three different binary field sizes using TSMC 90 $nm$ standard cell library from Artisan Components, and have been synthesized with a target 1.2 GHz system clock frequency using the Cadence Genus Synthesis tool. The proposed architecture offers 14%, 30%, and 19% reduction in average leakage, dynamic power, and area, respectively, compared to the state-of-the-art. Thus, the proposed architecture is better suited for energy-efficient portable systems, including wireless sensors.

Subject Keywords

Galois Field Multiplier, Synthesis, Irreducible, Low-Power, Area-Efficient, All-One Polynomial (AOP), Elliptic Curve Cryptography (ECC)

URI

https://hdl.handle.net/11511/69238

Collections

Northern Cyprus Campus, Thesis

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Citation Formats

S. Mohaghegh, “Low-power and area-efficient finite field arithmetic architecture based on irreducible all-one polynomials,” M.S. - Master of Science, Middle East Technical University, 2020.