Low-power and area-efficient finite field arithmeticarchitecture based on irreducible all-one polynomials

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2020-9

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Mohaghegh, Shima

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This thesis presents a low-power and area-efficient finite field multiplier based onirreducible all-one polynomials (AOP). The proposed organization implements theAOP multiplication algorithm in three stages, which are reduction network, ANDnetwork (multiplication), and three input XOR tree (accumulation), while state-of-the-art implementations distribute reduction, multiplication and accumulation opera-tions in a systolic array. The optimization reduces the overall number of sequentialelements and provides lower pipeline latency compared to literature. This leads tothe reduction of power dissipation and area for a system clock frequency. Both thepreviously reported and the proposed architectures have been implemented in Ver-ilog for three different binary field sizes using TSMC 90nmstandard cell libraryfrom Artisan Components, and have been synthesized with a target 1.2 GHz systemclock frequency using the Cadence Genus Synthesis tool. The proposed architec-ture offers 14%, 30%, and 19% reduction in average leakage, dynamic power, andarea, respectively, compared to the state-of-the-art. Thus, the proposed architecture isbetter suited for energy-efficient portable systems, including wireless sensors.

Subject Keywords

Elliptic curve cryptography (ECC), All-one polynomial (AOP), Area-efficient, Low-power, Irreducible, Synthesis, Galois field multiplier

URI

https://hdl.handle.net/11511/90128

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Northern Cyprus Campus, Thesis

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Citation Formats

S. Mohaghegh, “Low-power and area-efficient finite field arithmeticarchitecture based on irreducible all-one polynomials,” M.S. - Master of Science, Middle East Technical University, 2020.