An in-plane high-sensitivity, low-noise micro-g silicon accelerometer with CMOS readout circuitry

Date

2004-08-01

Author

Chae, J
Külah, Haluk
Najafi, K

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A high-sensitivity, low-noise in-plane (lateral) capacitive silicon microaccelerometer utilizing a combined surface and bulk micromachining technology is reported. The accelerometer utilizes a 0.5-mm-thick, 2.4 x 1.0 mm(2) proof-mass and high aspect-ratio vertical polysilicon sensing electrodes fabricated using a trench refill process. The electrodes are separated from the proof-mass by a 1.1-mum sensing gap formed using a sacrificial oxide layer. The measured device sensitivity is 5.6 pF/g. A CMOS readout circuit utilizing a switched-capacitor front-end Sigma - Delta modulator operating at 1 MHz with chopper stabilization and correlated double sampling technique, can resolve a capacitance of 10 aF over a dynamic range of 120 dB in a 1 Hz BW. The measured input referred noise floor of the accelerometer-CMOS interface circuit is 1.6mug/rootHz in atmosphere.

Subject Keywords

Mechanical Engineering, Electrical and Electronic Engineering

URI

https://hdl.handle.net/11511/38269

Journal

JOURNAL OF MICROELECTROMECHANICAL SYSTEMS

DOI

https://doi.org/10.1109/jmems.2004.832653

Collections

Department of Electrical and Electronics Engineering, Article

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Citation Formats

J. Chae, H. Külah, and K. Najafi, “An in-plane high-sensitivity, low-noise micro-g silicon accelerometer with CMOS readout circuitry,” JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, pp. 628–635, 2004, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/38269.