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FPGEN: A fast, scalable and programmable traffic generator for the performance evaluation of high-speed computer networks
Date
2011-12-01
Author
Sanli, Mustafa
Schmidt, Şenan Ece
Guran, Hasan Cengiz
Metadata
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This work is licensed under a
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License
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Testing today's high-speed network equipment requires the generation of network traffic which is similar to the real Internet traffic at Gbps line rates. There are many software-based traffic generators which can generate packets according to different stochastic distributions. However, they are not suitable for high-speed hardware test platforms. This paper describes FPGEN (Fast Packet GENerator), a programmable random traffic generator which is entirely implemented on FPGA (Field Programmable Gate Array). FPGEN can generate variable packet sizes and traffic with Poisson and Markov-modulated on-off statistics at OC-48 rate per interface. Our work that is presented in this paper includes the theoretical design of FPGEN, the hardware design of the FPGA-based traffic generator board (printed circuit board design and construction) and the implementation of FPGEN on FPGA. Our experimental study demonstrates that FPGEN can achieve both the desired rate and statistical properties for the generated traffic.
Subject Keywords
Modelling and Simulation
,
Computer Networks and Communications
,
Hardware and Architecture
,
Software
URI
https://hdl.handle.net/11511/38553
Journal
PERFORMANCE EVALUATION
DOI
https://doi.org/10.1016/j.peva.2011.07.003
Collections
Department of Electrical and Electronics Engineering, Article
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M. Sanli, Ş. E. Schmidt, and H. C. Guran, “FPGEN: A fast, scalable and programmable traffic generator for the performance evaluation of high-speed computer networks,”
PERFORMANCE EVALUATION
, pp. 1276–1290, 2011, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/38553.