Hardware Accelerators for Cloud Computing: Features and Implementation

Date

2021-01-01

Author

Tirlioglu, Anil
Demir, Omer Bayram
Yazar, Alper
Schmidt, Şenan Ece

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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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In this paper, hardware accelerator (FHA) applications realized on FPGA that can be offered as a service in cloud computing systems are discussed. It is necessary to know the hardware resources used by FHA applications and the performance they provide for the efficient meeting of the user requests and effective resource planning. To this end, the first contribution of this paper is to provide a compilation of the literature on the features of frequently used hardware accelerators (matrix multiplication, face detection, FFT) in the last three years, based on common parameters and metrics. The numerical values we provide can be used for cloud resource allocation and creation of sample cloud workloads. The second contribution of our paper is the implementation of the Canny edge detector, a sample hardware accelerator implemented in HLS (High-level Synthesis), using an open source library. In this way, the work flow for the implementation and operation of the hardware accelerator together with its performance are presented.

Subject Keywords

hardware accelerator, Canny edge detection, FPGA, cloud computing

URI

https://hdl.handle.net/11511/100502

DOI

https://doi.org/10.1109/siu53274.2021.9478015

Conference Name

29th IEEE Conference on Signal Processing and Communications Applications (SIU)

Collections

Department of Electrical and Electronics Engineering, Conference / Seminar

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Citation Formats

A. Tirlioglu, O. B. Demir, A. Yazar, and Ş. E. Schmidt, “Hardware Accelerators for Cloud Computing: Features and Implementation,” presented at the 29th IEEE Conference on Signal Processing and Communications Applications (SIU), ELECTR NETWORK, 2021, Accessed: 00, 2022. [Online]. Available: https://hdl.handle.net/11511/100502.