HARDWARE ACCELERATED PACKET PARSERS AND DEPARSERS FOR HIGH-THROUGHPUT FLOW CLASSIFICATION IN COMPUTER NETWORKS: DESIGN, IMPLEMENTATION AND EVALUATION

Date

2024-9-12

Author

Demir, Omer Bayram

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Handling the increasing data rates and diverse traffic patterns of 5G networks requires high-performance packet processing. Packet parsers play a crucial role in identifying and parsing relevant information from the packets. Designing efficient packet parsers is challenging due to the diverse parsing graphs that emerge from computer networking for various applications. Including new protocols introduced by technologies like 5G networking. As older implementations become insufficient, new designs are continually needed. Software-defined networking (SDN) technology increases the configurability of computer networks and the lifetime of network devices. Fully utilizing SDN networks requires configurable networking devices. In this thesis work, we present the design and implementation of an efficient packet parser and deparser tailored for the User Plane Function (UPF) block in a 5G networking plane, leveraging the reconfigurability and high throughput of Field Programmable Gate Arrays (FPGAs). The main contributions of this work include the design and FPGA implementation of an efficient packet parser and deparser for N3 and N6 interfaces for a UPF block, which can parse the packets fitting the parse graph for standard 5G network packets presented later in this thesis. A novel checksum modifier for IPv4 packets was introduced. A packet sanity checker to analyze the corrections of the packets to be used in SystemVerilog testbenches is developed to increase the testing coverages for networking applications in general. Synthesis and simulation results for the designed hardware in the scope of this thesis work are also introduced at the end of the thesis.

Subject Keywords

5G, Network, Parser, FPGA, High-throughput

URI

https://hdl.handle.net/11511/110997

Collections

Graduate School of Natural and Applied Sciences, Thesis