On an Efficient Implementation of Combined True Random Number Generator and Physically Unclonable Function on a SoC FPGA

Date

2024-9

Author

Yılmaz, Yunus Emre

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True Random Number Generators (TRNGs) and Physically Unclonable Functions (PUFs) are two basic and useful primitives in designing cryptographic systems. TRNGs must be invariably random, while PUFs must have repetitive results and instance-specific randomness. In this work, these primitives are implemented in a System-on-Chip Field-Programmable Gate Array (SoC FPGA), or simply SoC. Phase-Locked Loops (PLLs) are essential components in both FPGAs and SoCs, widely implemented for various functions. Within these devices, PLLs offer a promising method for generating random numbers. Due to their isolated operation, broad utilization, and strong entropy generation, as validated by prior research, PLLs integrated into FPGAs or SoCs serve as highly effective foundations for PLL-based true random number generators (PLL-TRNGs). This makes PLL-TRNGs a particularly viable solution for generating secure random numbers in such architectures. The parameter selection in PLL-TRNG is a very critical process since it requires yielding both a sufficient entropy rate and an adequate output bit rate. Hence, in the first part of this thesis, a parameter selection algorithm based on the backtracking method in the literature is chosen and adapted to our selected SoC. In addition to these, a novel methodology is proposed to enhance the rate of random data bit generation of PLL-TRNG by using extra PLLs with a specific interconnection while preserving entropy characteristics. Performance metrics are rigorously evaluated against the criteria set by the German Federal Office for Information Security (BSI) AIS-20/31 Tests and compared to the works in the literature. Other than TRNGs, designing a secure PUF is another motivation for this thesis. The Arbiter PUF, recognized as the first silicon PUF, is capable of generating a substantial number of secret keys instantaneously based on the input, all while maintaining a lightweight design. This advantageous characteristic makes it particularly well-suited for device authentication in applications with constrained resources, especially for Internet of Things (IoT) devices. Despite these advantages, arbiter PUFs are vulnerable to machine learning (ML) attacks. Hence, those arbiter PUF designs are improved to achieve increased resistance against such attacks. These improvements aim to increase resilience against ML attacks while maintaining usefulness and efficiency for IoT applications. In the second part of this thesis, a machine-learning-resistant 32-bit and 64-bit component-differentially challenged XOR Arbiter PUF (CDC-XPUF) is implemented based on a design found in the literature. The 32-bit and 64-bit 7-stream CDC-7-XPUFs are evaluated using PUF metrics in the literature, namely steadiness, correctness, diffuseness, uniformity, and uniqueness. Additionally, the utilization ratios for both TRNG and PUF implementations are presented. In the last part of this thesis, PLL-TRNG with four PLLs (4-PLL-TRNG) and 64-bit 7-stream CDC-XPUF (CDC-7-XPUF) is combined so that they can work together. The random numbers generated by 4-PLL-TRNG are utilized by CDC-7-XPUF to generate other challenges from the main challenge. All the tests applied to TRNG and PUF are also applied to this combined design, and it is shown that that combined design is a suitable candidate to use in an IoT system. Consequently, a total of three different configurations, two of which are discrete implementations of PLL-TRNG and CDC-XPUF and one of which is a combined implementation of these PLL-TRNG and CDC-XPUF, are implemented. All of the tests are implemented using the ZC702 Rev1.1 Evaluation Board, which features the Xilinx Zynq 7020 SoC, and utilizes a configuration involving three boards for experimental validation.

Subject Keywords

True random number generator (TRNG), Physically unclonable function (PUF), Field-programmable gate array (FPGA), System-on-chip (SoC), Phase-locked loop (PLL), Component-differentially challenged XOR arbiter PUF (CDC-XPUF)

URI

https://hdl.handle.net/11511/111066

Collections

Graduate School of Applied Mathematics, Thesis