HARDWARE ACCELERATORS FOR HIGH THROUGHPUT PACKET CLASSIFICATION IN COMPUTER NETWORKS

Date

2024-8-27

Author

Arkadaş, Doğu Erkan

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This thesis proposes two separate approaches for the packet classification problem, one implemented on an FPGA and the other on a GPU. Packet classification is a task performed by network routers for various functions. With the increasing rule set and user traffic size, packet classifiers must be faster and more scalable. The first proposed approach, BVGPU, is developed using CUDA. It fully utilizes the high-speed memory bus of NVIDIA GPUs and employs a bit-vector-based algorithm using the extended FSBV algorithm. BVGPU is implemented on an RTX 3080 10GB video card. Evaluations demonstrate state-of-the-art throughput for 5-tuple classification for 1K and 10K-scale rule sets of 2575 and 770 MPPs, respectively, with average latencies of 9 μs and 13.42 μs. To the best of our knowledge, for 1K-scale rule sets, BVGPU's throughput is the highest in the literature of any packet classification approach. The second proposed approach, BVFPGA, iterates on the StrideBV algorithm, featuring a more optimized pipeline with significantly reduced fanout. High fanout results in lower clock speeds, higher power consumption, and greater use of routing resources. BVFPGA reduces fanout by a user-defined factor, using resources comparable to the StrideBV pipeline. This reduction enables easier implementation without sacrificing performance and clock cycle latency, achieving 290 MHz frequencies in initial tests corresponding to 580 MPPs throughput with less than 0.15 μs latency. BVFPGA provides robust control hardware for rule update operations and an end-to-end control message structure for runtime control operations.

Subject Keywords

Packet classification, Parallel computing, CUDA, FPGA, GPU, 5-tuple

URI

https://hdl.handle.net/11511/111347

Collections

Graduate School of Natural and Applied Sciences, Thesis