Design and Implementation of a Fast, Platform-Adaptive, AIS-20/31 Compliant PLL-Based True Random Number Generator on a Zynq 7020 SoC FPGA

Date

2024-01-01

Author

Yayla, Oğuz
Yılmaz, Yunus Emre

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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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Phase-locked loops (PLLs) integrated within field-program-mable gate arrays (FPGAs) or System-on-Chip FPGAs (SoCs) represent a promising approach for generating random numbers. Their widespread deployment, isolated functionality within these devices, and robust entropy, as demonstrated in prior studies, position PLL-based true random number generators (PLL-TRNGs) as highly viable solutions for this purpose. This study explicitly examines PLL-TRNG implementations using the ZC702 Rev1.1 Evaluation Board featuring the Zynq 7020 SoC from Xilinx, utilizing a configuration involving three such boards for experimental validation. Parameters governing the PLL-TRNG are optimized using a backtracking algorithm. Additionally, a novel methodology is proposed to enhance the rate of random data bit generation while preserving entropy characteristics. Performance metrics are rigorously evaluated against the criteria set by the German Federal Office for Information Security (BSI) AIS-20/31 Tests, accompanied by detailed descriptions of the implementation process.

Subject Keywords

AIS-20/31, PLL-TRNG, random number generation

URI

https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85210147759&origin=inward
https://hdl.handle.net/11511/112771

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Graduate School of Applied Mathematics, Conference / Seminar