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Optimizing core signal processing functions on a superscalar SIMD architecture

Uslu, Çağrı
Digital Signal Processing (DSP) is the basis of many technologies, such as Image Processing, Speech Recognition, Radars, etc. Use of electronic devices such as smart- phones, smartwatches, self-driving cars and autonomous robots that take advantage of these technologies becomes widespread and hence it is more critical than ever for these technologies to be realized with high efficiency on cheaper and less power- hungry devices. Cortex-A15 processor architecture is one of the solutions from ARM to this requirement. Therefore, it is worth to optimize certain DSP functions on the Cortex-A15. In this thesis, four commonly used DSP operations are implemented on an ARM Cortex-A15 processor, heavily utilizing the vector co-processor NEON. The optimized operations are Matrix Addition, Matrix Multiplication, Convolution, and Fourier Transform. Although numerous DSP libraries implement these operations, they are not tailored to a specific processor. The functions implemented in this thesis aim to be most efficient on Cortex-A15, which is a superscalar, out-of-order executing processor. All types of processors may suffer from pipeline stalls. However, unlike scalar processors, superscalar processors may achieve a superscalar performance even in the presence of pipeline stalls. This could be accomplished by utilizing the execution units of the processor better. One way of possibly increasing the utilization of the execution units is instruction reordering. To reorder instructions optimally, one must know certain specifications of the architecture. To discover one of those specifications, i.e. the cost of instructions in clock cycles, a method is developed for performing the appropriate time measurements. Additionally, a set of guidelines for instruction reordering is conceived. Using these guidelines, among other optimization techniques, the DSP functions mentioned earlier are manually optimized to achieve a high execution performance.