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Substation level state estimation and topology error processing

2020
Saruhan, Erdi
The Phasor Measurement Units (PMUs) are recently utilized in the real-time monitoring, control and protection applications in electrical power systems. PMUs contribute the better understanding of modern power systems by rendering time synchronized voltage and current measurements thanks to their high-resolution and high-precision compared to the conventional SCADA measurements. State estimation is one of the most important monitoring means in power systems. State estimation can be performed solely at substation level by utilization of synchrophasor PMU measurements. By substation level state estimation, erroneous measurements can be filtered at substation level and the computational burden of control centers may be reduced. Topological errors cause biased state estimates, which may have catastrophic results for power system operation. Therefore, detection and identification of topological errors is critical. Despite its criticality, topological error processing has a significant computational burden for centralized control centers. Thus, performing topology error processing task at substation level can improve the computational performance. Performing state estimation and topology error processing tasks at substation level will improve the monitoring capabilities and the situational awareness of electric power systems. This thesis proposes a substation level state estimator and topology error processor. The proposed method relies on the presence of PMU measurements and solves the estimation problem with the well-known Weighted Least Squares (WLS) estimator. The proposed method is validated with real substation topologies. The method can provide accurate system state estimates, filter the bad data and detect topological inconsistencies at the substation.