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Complete test generation method for all stuck-at faults in combinational circuits

1990-5
GURAN, HASAN
HALICI, UGUR
In combinational logic circuits the generation of complete fault detection test sets requires the determination of the complete test sets of all possible stuck-at faults. In this study, an efficient procedure is developed for finding all the complete test sets of all possible single stuck-at faults in a combinational circuit. The developed procedure primarily uses the properties of logic gates. An example is solved by the use of the developed procedure.