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Complete test generation method for all stuck-at faults in combinational circuits
Date
1990-5
Author
GURAN, HASAN
HALICI, UGUR
Metadata
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In combinational logic circuits the generation of complete fault detection test sets requires the determination of the complete test sets of all possible stuck-at faults. In this study, an efficient procedure is developed for finding all the complete test sets of all possible single stuck-at faults in a combinational circuit. The developed procedure primarily uses the properties of logic gates. An example is solved by the use of the developed procedure.
Subject Keywords
Electrical and Electronic Engineering
URI
https://hdl.handle.net/11511/51367
Journal
International Journal of Electronics
DOI
https://doi.org/10.1080/00207219008921209
Collections
Department of Electrical and Electronics Engineering, Article
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H. GURAN and U. HALICI, “Complete test generation method for all stuck-at faults in combinational circuits,”
International Journal of Electronics
, pp. 657–666, 1990, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/51367.