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Discussion on stuck-at faults in combinational circuits
Date
1989-7
Author
Halıcı, Uğur
Metadata
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In combinational logic circuits, stuck-at faults are permanent faults that are modelled as logical problems. In this study, a new method for finding the complete test set of single stuck-at faults is presented. A novel algorithm based on the given discussion is developed and applied to an example.
Subject Keywords
Electrical and electronic engineering
URI
https://hdl.handle.net/11511/52079
Journal
International Journal of Electronics
DOI
https://doi.org/10.1080/00207218908921049
Collections
Department of Electrical and Electronics Engineering, Article
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U. Halıcı, “Discussion on stuck-at faults in combinational circuits,”
International Journal of Electronics
, pp. 7–14, 1989, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/52079.