A real time, low latency, FPGA implementation of the 2-D discrete wavelet transformation for streaming image applications

Date

2003-09-06

Author

Benderli, O
Tekmen, YC
Ismailoglu, N

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In this paper, we present an architecture and a hardware implementation of the 2-D Discrete Wavelet Transformation (DWT) for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The architecture is especially suited for multi-spectral imager systems, such as on board an imaging satellite, however can be used in any application where time to next image constraints require real-time processing of multiple images. The latency that is introduced as the images stream through the DWT filter and the amount of locally stored image data is a function of the image and tile size. For an n(1) x n(2) size image processed using (n(1)/k(1)) x (n(2)/k(2)) sized tiles the latency is equal to the time elapsed to accumulate a (1/k(1)) portion of one image. In addition, a (2/k(1)) portion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG2000 compression system designed as a payload for a Low Earth Orbit (LEO) micro-satellite, which will be launched in August 2003.

Subject Keywords

Efficient realizations

URI

https://hdl.handle.net/11511/67199

DOI

https://doi.org/10.1109/dsd.2003.1231971

Collections

Department of Computer Engineering, Conference / Seminar

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Citation Formats

O. Benderli, Y. Tekmen, and N. Ismailoglu, “A real time, low latency, FPGA implementation of the 2-D discrete wavelet transformation for streaming image applications,” 2003, p. 384, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/67199.