A real-time, low-latency, FPGA implementation of the two dimensional discrete wavelet transform

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2003

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Benderli, Oğuz

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This thesis presents an architecture and an FPGA implementation of the two dimensional discrete wavelet transformation (DWT) for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The architecture is especially suited for multi-spectral imager systems, such as on board an imaging satellite, however can be used in any application where time to next image constraints require real-time processing of multiple images. The latency that is introduced as the images stream through the iii DWT module and the amount of locally stored image data, is a function of the image and tile size. For an n1 ₉ n2 size image processed using (n1/k1) ₉ (n2/k2) sized tiles the latency is equal to the time elapsed to accumulate a (1/k1) portion of one image. In addition, a (2/k1) portion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG 2000 compression system designed as a payload for a low earth orbit (LEO) micro-satellite to be launched in September 2003. The architecture can achieve a throughput of up to 160Mbit/s. The latency introduced is 0.105 sec (6.25% of total transmission time) for tile sizes of 256₉256. The local storage size required for the tiling operation is 2 MB. The internal storage requirement is 1536 pixels. Equivalent gate count for the design is 292,447

Subject Keywords

JPEG., Image processing

URI

http://etd.lib.metu.edu.tr/upload/1056282/index.pdf
https://hdl.handle.net/11511/13509

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Graduate School of Natural and Applied Sciences, Thesis

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Citation Formats

O. Benderli, “A real-time, low-latency, FPGA implementation of the two dimensional discrete wavelet transform,” M.S. - Master of Science, Middle East Technical University, 2003.