Investigation of a method to identify energy efficient organization of compression unit in parallel tree multipliers

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2018-1

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Rashid, Muhammad Saleh

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In this study, high-performance integer multipliers extensively used in digital signal processing are investigated in the context of energy-aware system organization. Among different functional blocks in an integer multiplier, the compression unit is primarily targeted for optimization as the largest section of the multiplier with significant energy consumption. Five different realizations of the most popular Wallace tree are investigated in this work, which consists of Dual Pass Logic (DPL) circuit implementations based on (3,2) counters, 4:2 compressors, 5:2 compressors, 6:2 compressors, and hybrid of (7,3) and (3,2) counters. Multiplier energy consumption highly depends on the type, efficiency, and a number of counters and compressors in the compression block, as well as connectivity and placement of these blocks. Therefore, the study investigates these aspects separately. Firstly, individual compressor and counter modules are implemented using Dual Pass Logic (DPL) circuit style in 180nm process technology to be available in a common library. A new metric is proposed for the energy efficiency of the individual compressor or counter modules and is quantified through circuit simulations. Each Wallace tree organization to be compared is designed in various sizes using the library. Theoretical worst delay path in each organization is verified through simulations using a large vector set. Then, a new method named System Compression Energy Efficiency Score (SCEES) is proposed, to quantitatively predict the ranking of different multiplier organizations in terms of energy efficiency. Extensive circuit simulations are performed to verify the effectiveness of the proposed method and metric, and the output data is post-processed using MATLAB. The analysis results in a refined energy aware methodology to select the most appropriate compression blocks to achieve energy efficiency for a particular multiplier size without going through the cumbersome steps in custom system design and simulations.

Subject Keywords

Compression Circuits, VLSI, Energy, Delay, Integer Multiplication

URI

https://hdl.handle.net/11511/69802

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Northern Cyprus Campus, Thesis

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Citation Formats

M. S. Rashid, “Investigation of a method to identify energy efficient organization of compression unit in parallel tree multipliers,” M.S. - Master of Science, Middle East Technical University, 2018.