Date

2015-6

Author

Ercan, Furkan

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Threshold detection is a fundamental logic function that has broad use in arithmetic processors, and other digital applications. Thus, any improvement in threshold detection in terms of power and/or delay contributes significantly to the field of digital circuit design. A recently reported parallel integer multiplier architecture, ABACUS, uses column compression networks to compress partial products through the final addition network. Architecture of column compression network of ABACUS is suitable for threshold logic use. Architecture of ABACUS enables a higher order of optimization with the use of threshold logic than conventional multipliers. In this study, we investigate the opportunity to optimize power-delay performance of ABACUS through threshold detection circuits in order to close a previously identified gap with Wallace Tree Multiplier (WTM). We study digital (CMOS-based) threshold detection solutions that are Compound-CMOS, transmission-gate, gate-level based, as well as analog solutions which are voltage-, current- and charge-based designs. Solutions are compared first for power-delay performance as the number of inputs and threshold values change. Threshold logic that provides the best power-delay product is then used to implement the ABACUS multiplier, which is compared with the conventional Wallace Tree Multiplier in terms of power-delay performance. At the end of this work, (i) accurate trend-lines were extracted to project best threshold logic circuit implementations as the number of inputs grows, (ii) solutions were used in a novel multiplication circuit (ABACUS) in order to measure performance in application, (iii) pre-layout, post-layout simulations and on-chip measurements for ABACUS architecture with threshold logic was presented to demonstrate that the performance gap with basic WTM implementation has indeed been closed through threshold logic. Further optimizations for better yield on power-delay product were also addressed.

Subject Keywords

Threshold Logic, VLSI, Power, Performance, Delay, Integer Multiplication

URI

https://hdl.handle.net/11511/69834

Collections

Northern Cyprus Campus, Thesis