Layout Based Ultra-Fast Short-Circuit Protection Technique for Parallel Connected GaN HEMTs

Gallium Nitride Enhancement-Mode High Electron Mobility Transistors (GaN HEMTs) help to achieve high power density converter circuits thanks to their superior efficiency, higher switching speed and small package size. However, increased switching speed results in a sharp increase in short circuit (SC) current under a shoot-through fault with respect to other type of devices. GaN HEMTs can withstand the SC current only for several hundred nanoseconds. Therefore, fast SC protection solutions are critical for protecting power circuits. In this paper, the voltage induced by high slew rate of SC current on the high frequency power loop inductance resulting from the printed circuit board (PCB) layout is sensed to implement an ultra-fast short-circuit protection technique. The proposed technique does not increase circuit parasitics and provides flexibility in layout design that makes it suitable for parallel connected GaN HEMTs, which require symmetric layout design for equal current sharing. A multi-pulse test is conducted under 1.56 MHz switching frequency, 400 VDC bus voltage and 40 A load current by using parallel connected GaN HEMTs in a half-bridge configuration to verify the robustness and reliability of the proposed protection technique. Experimental results show that the proposed protection technique is able to detect SC fault within 40 ns and fault is completely cleared with a soft turn-off in 250 ns.


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Citation Formats
F. Karakaya and O. Keysan, “Layout Based Ultra-Fast Short-Circuit Protection Technique for Parallel Connected GaN HEMTs,” IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, pp. 1–1, 2021, Accessed: 00, 2021. [Online]. Available: