Pipelined design approach to microprocessor architectures a partial implementation : mips pıpelined architecture on fpga

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Date

2005

Author

Altıniğneli, Muzaffer Can

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This thesis demonstrate how pipelining in a RISC processor is achieved by implementing a subset of MIPS R2000 instructions on FPGA. Pipelining, which is one of the primary concepts to speed up a microprocessor is emphasized throughout this thesis. Pipelining is fundamentally invisible for high level programming language user and this work reveals the internals of microprocessor pipelining and the potential problems encountered while implementing pipelining. The comparative and quantitative flow of this thesis allows to understand why pipelining is preferred instead of other possible implementation schemes. The methodology for programmable logic development and the capabilities of programmable logic devices are also given as background information. This thesis can be the starting point and reference for programmers who are willing to get familiar with microprocessors and pipelining.

Subject Keywords

Computer engineering.

URI

http://etd.lib.metu.edu.tr/upload/12606778/index.pdf
https://hdl.handle.net/11511/15630

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Graduate School of Natural and Applied Sciences, Thesis

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Citation Formats

M. C. Altıniğneli, “Pipelined design approach to microprocessor architectures a partial implementation : mips pıpelined architecture on fpga,” M.S. - Master of Science, Middle East Technical University, 2005.