Pipelined design approach to microprocessor architectures a partial implementation : mips pıpelined architecture on fpga

Altıniğneli, Muzaffer Can
This thesis demonstrate how pipelining in a RISC processor is achieved by implementing a subset of MIPS R2000 instructions on FPGA. Pipelining, which is one of the primary concepts to speed up a microprocessor is emphasized throughout this thesis. Pipelining is fundamentally invisible for high level programming language user and this work reveals the internals of microprocessor pipelining and the potential problems encountered while implementing pipelining. The comparative and quantitative flow of this thesis allows to understand why pipelining is preferred instead of other possible implementation schemes. The methodology for programmable logic development and the capabilities of programmable logic devices are also given as background information. This thesis can be the starting point and reference for programmers who are willing to get familiar with microprocessors and pipelining.


Implementation and simulation of mc68hc11 microcontroller unit using systemc for co-design studies
Tuncalı, Cumhur Erkan; Aşkar, Murat; Department of Electrical and Electronics Engineering (2007)
In this thesis, co-design and co-verification of a microcontroller hardware and software using SystemC is studied. For this purpose, an MC68HC11 microcontroller unit, a test bench that contains input and output modules for the verification of microcontroller unit are implemented using SystemC programming language and a visual simulation program is developed using C# programming language in Microsoft .NET platform. SystemC is a C++ class library that is used for co-designing hardware and software of a system...
A dependable computing application
Güngör, Uğur; Güran, Hasan Cengiz; Department of Electrical and Electronics Engineering (2005)
This thesis focuses on fault tolerance which is kind of dependable computing implementation. It deals with the advantages of fault tolerance techniques on Single Event Upsets (SEU) occurred in a Field Programmable Gate Array (FPGA). Two fault tolerant methods are applied to floating point multiplier. Most common SEU mitigation method is Triple Modular Redundancy (TMR). So, two fault tolerance methods, which use TMR, are tested. There are three printed circuit boards (PCBs) and one user interface software in...
Parallel Scalable PDE Constrained Optimization Antenna Identification in Hyperthermia Cancer Treatment Planning
SCHENK, Olaf; Manguoğlu, Murat; CHRİSTEN, Matthias; SATHE, Madan (Springer Science and Business Media LLC, 2009-01-01)
We present a PDE-constrained optimization algorithm which is designed for parallel scalability on distributed-memory architectures with thousands of cores. The method is based on a line-search interior-point algorithm for large-scale continuous optimization, it is matrix-free in that it does not require the factorization of derivative matrices. Instead, it uses a new parallel and robust iterative linear solver on distributed-memory architectures. We will show almost linear parallel scalability results for t...
SystemC implementation with analog mixed signal modeling for a microcontroller
Mert, Yakup Murat; Aşkar, Murat; Department of Electrical and Electronics Engineering (2007)
In this thesis, an 8-bit microcontroller, PIC 16F871, has been implemented using SystemC with classical hardware design methods. Analog modules of the microcontroller have been modeled behaviorally with SystemC-AMS which is the analog and mixed signal extensions for the SystemC. SystemC-AMS provides the capability to model non-digital modules and synchronization with the SystemC kernel. In this manner, electronic systems that have both digital and analog components can be described and simulated very effect...
Performance analysis of a power aware routing protocol for ad hoc networks
Yazıcı, Mehmet Akif; Bilgen, Semih; Department of Electrical and Electronics Engineering (2006)
In this thesis, performance of the Contribution Reward Routing Protocol with Shapley Value (CAP-SV), a power-aware routing protocol for ad hoc networking is analyzed. Literature study on ad hoc network routing and ower-awareness is given. The overhead induced by the extra packets of the redirection mechanism of CAP-SV is formulized and the factors affecting this overhead are discussed. Then, the power consumption of CAP-SV is analytically analized using a linear power consumption model. It is shown that CAP...
Citation Formats
M. C. Altıniğneli, “Pipelined design approach to microprocessor architectures a partial implementation : mips pıpelined architecture on fpga,” M.S. - Master of Science, Middle East Technical University, 2005.