New montgomery modular multıplier architecture

Çiftçibaşı, Mehmet Emre
This thesis is the real time implementation of the new, unified field, dualا radix Montgomery modular multiplier architecture presented by Savaş et al, for performance comparison with standard Montgomery multiplication algorithms. The unified field architecture operates in both GF(p) and GF(2n). The dual radix capability enables processing of two bits of the multiplier in every clock cycle in GF(2n) mode, while one bit of the multiplier is processed in GF(p) mode. The new architecture is implemented in a Xilinx FPGA on the custom printed circuit board. The windows user interface is developed in Borland Builder environment and the ethernet interface is implemented by Ubicom IP2022 controller. The algorithms are compared from operating clock frequency, silicon area cost and multiplication time perspectives. The new architecture multiplies two times faster in GF(p) and four times faster in GF(2n), compared to the previous architectures as expected. The operand length is increased from 8 bits to 1024 bits, with the compromise of decreasing the operating clock frequency from 150 Mhz down to 15 Mhz.


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Citation Formats
M. E. Çiftçibaşı, “New montgomery modular multıplier architecture,” M.S. - Master of Science, Middle East Technical University, 2005.