SystemC implementation of a risc-based microcontroller architecture

Date

2007

Author

Zengin, Salih

Metadata

Show full item record

Item Usage Stats

20
views

86
downloads

Cite This

Increasing the complexity of modern electronic systems leads to Electronic System Level (ESL) modeling concept, which supports hardware and software co-design and co-verification environment in a single framework. SystemC language, which is an IEEE approved electronic design standard for system design and verification processes, provides such an environment by supporting a wide range of abstraction levels from system-level to register-transfer level (RTL). In this thesis, two different models of a processor core, whose instruction set architecture (ISA) is compatible with 16-bit TI MSP430 microcontroller, are designed by employing the classical hardware modeling capability of the SystemC language. With its well-designed orthogonal instruction set, elegant addressing modes, useful constant generators and flexible von-Neumann architecture, 16-bit RISC-like processor of the MSP430 microcontroller is an ideal selection for the system-on-a-chip (SoC) designs. Instruction set and addressing modes of the designed processors are simulated thoroughly. In addition, original 16-bit and 32-bit cyclic redundancy code (CRC) programs are used in order to verify the processor cores. In this study, SystemC to hardware flow is also illustrated by synthesizing the Arithmetic and Logic Unit (ALU) part of the processor into a Xilinx-based hardware.

Subject Keywords

Video Compression.

URI

http://etd.lib.metu.edu.tr/upload/2/12608083/index.pdf
https://hdl.handle.net/11511/16934

Collections

Graduate School of Natural and Applied Sciences, Thesis