Show/Hide Menu
Hide/Show Apps
Logout
Türkçe
Türkçe
Search
Search
Login
Login
OpenMETU
OpenMETU
About
About
Open Science Policy
Open Science Policy
Open Access Guideline
Open Access Guideline
Postgraduate Thesis Guideline
Postgraduate Thesis Guideline
Communities & Collections
Communities & Collections
Help
Help
Frequently Asked Questions
Frequently Asked Questions
Guides
Guides
Thesis submission
Thesis submission
MS without thesis term project submission
MS without thesis term project submission
Publication submission with DOI
Publication submission with DOI
Publication submission
Publication submission
Supporting Information
Supporting Information
General Information
General Information
Copyright, Embargo and License
Copyright, Embargo and License
Contact us
Contact us
Design and performance of capacity approaching irregular low-density parity-check codes
Download
index.pdf
Date
2009
Author
Bardak, Erinç Deniz
Metadata
Show full item record
Item Usage Stats
211
views
48
downloads
Cite This
In this thesis, design details of binary irregular Low-Density Parity-Check (LDPC) codes are investigated. We especially focus on the trade-off between the average variable node degree, wa, and the number of length-6 cycles of an irregular code. We observe that the performance of the irregular code improves with increasing wa up to a critical value, but deteriorates for larger wa because of the exponential increase in the number of length-6 cycles. We have designed an irregular code of length 16,000 bits with average variable node degree wa=3.8, that we call ‘2/3/13’ since it has some variable nodes of degree 2 and 13 in addition to the majority of degree-3 nodes. The observed performance is found to be very close to that of the capacity approaching commercial codes. Time spent for decoding 50,000 codewords of length 1800 at Eb/No=1.6 dB for an irregular 2/3/13 code is measured to be 19% less than that of the regular (3, 6) code, mainly because of the smaller number of decoding failures.
Subject Keywords
Electrical engineering.
,
Telecommunication.
URI
http://etd.lib.metu.edu.tr/upload/12611084/index.pdf
https://hdl.handle.net/11511/18849
Collections
Graduate School of Natural and Applied Sciences, Thesis
Suggestions
OpenMETU
Core
Design and fpga implementation of an efficient deinterleaving algorithm
Olgun, Muhammet Ertuğ; Akar, Gözde; Department of Electrical and Electronics Engineering (2008)
In this work, a new deinterleaving algorithm that can be used as a part of an ESM system and its implementation by using an FPGA is studied. The function of the implemented algorithm is interpreting the complex electromagnetic military field in order to detect and determine different RADARs and their types by using incoming RADAR pulses and their PDWs. It is assumed that RADAR signals in the space are received clearly and PDW of each pulse is generated as an input to the implemented algorithm system. Cluste...
Computation of radar cross sections of complex targets by physical optics with modified surface normals
Durgun, Ahmet Cemal; Kuzuoğlu, Mustafa; Department of Electrical and Electronics Engineering (2008)
In this study, a computer code is developed in MATLAB® to compute the Radar Cross Section (RCS) of arbitrary shaped complex targets by using Physical Optics (PO) and Modified PO. To increase the computational efficiency of the code, a novel fast integration procedure for oscillatory integrals, called Levin’s integration, is applied to PO integrals. In order to improve the performance of PO near grazing angles and to model diffraction effects, a method called PO with Modified Surface Normal Vectors is implem...
Fpga implementation of jointly operating channel estimator and parallelized decoder
Kılcıoğlu, Çağlar; Yılmaz, Ali Özgür; Department of Electrical and Electronics Engineering (2009)
In this thesis, implementation details of a joint channel estimator and parallelized decoder structure on an FPGA-based platform is considered. Turbo decoders are used for the decoding process in this structure. However, turbo decoders introduce large decoding latencies since they operate in an iterative manner. To overcome that problem, parallelization is applied to the turbo codes and the resulting parallel decodable turbo code (PDTC) structure is employed for coding. The performance of a PDTC decoder and...
Verification of Modular Diagnosability With Local Specifications for Discrete-Event Systems
Schmidt, Klaus Verner (Institute of Electrical and Electronics Engineers (IEEE), 2013-09-01)
In this paper, we study the diagnosability verification for modular discrete-event systems (DESs), i.e., DESs that are composed of multiple components. We focus on a particular modular architecture, where each fault in the system must be uniquely identified by the modular component where it occurs and solely based on event observations of that component. Hence, all diagnostic computations for faults to be detected in this architecture can be performed locally on the respective modular component, and the obt...
Direction finding for coherent, cyclostationary signals via a uniform circular array
Atalay Çetinkaya, Burcu; Koç, Arzu; Department of Electrical and Electronics Engineering (2009)
In this thesis work, Cyclic Root MUSIC method is integrated with spatial smoothing and interpolation techniques to estimate the direction of arrivals of coherent,cyclostationary signals received via a Uniform Circular Array (UCA). Cyclic Root MUSIC and Conventional Root MUSIC algorithms are compared for various signal scenarios by computer simulations. A cyclostationary process is a random process with probabilistic parameters, such as the autocorrelation function, that vary periodically with time. Most of ...
Citation Formats
IEEE
ACM
APA
CHICAGO
MLA
BibTeX
E. D. Bardak, “Design and performance of capacity approaching irregular low-density parity-check codes,” M.S. - Master of Science, Middle East Technical University, 2009.
