Design and implementation of hardware architectures for high-speed IP address lookup

Ayyildiz, Nizam
IP address lookup modules for backbone routers should store 100Ks of entries, find the longest prefix match (LPM) for each incoming packet at 10s of Gbps line speed and support thousands of lookup table updates each second. It is desired that these updates are non-blocking, that is without disrupting the ongoing lookups. Furthermore, considering the increasing line rates and table sizes, the scalability of the design is very important. The goal of this thesis is developing hardware IP lookup architectures that perform single clock cycle lookups and non-blocking updates that are entirely carried out on hardware. To this end, we propose a custom TCAM architecture for IP lookup that we call S-DIRECT-Scalable and Dynamically REConfigurable TCAM and a complete IP lookup solution that utilizes di_erent types of memory that we call SHIP-Scalable Highspeed IP lookup. Both S-DIRECT and SHIP feature a modular design that allows seamless scaling to di_erent table sizes. We implement the developed architectures on FPGA with a resource e_cient realization and provide the hardware requirements for implementation on other platforms. We demonstrate the viability of our architectures with a full implementation on FPGA that can store contemporary routing tables.
Citation Formats
N. Ayyildiz, “Design and implementation of hardware architectures for high-speed IP address lookup,” Ph.D. - Doctoral Program, Middle East Technical University, 2013.