A Dynamic memory manager for FPGA applications/

Özer, Cenk
Recently, FPGAs are shipped with a large amount of internal memory (block RAM) sufficient to perform many complex computations without a need for off-chip memory. However, block RAMs (BRAMs) of FPGAs should be used efficiently especially for computations that need dynamic management of the memory. Thus, within the scope of this thesis work, a dynamic memory manager (DMM) unit is designed with an objective of meeting memory requests with a low fragmentation at runtime for FPGA applications. The unit is designed to have a bounded response time for dynamic memory requests to be suitable for real time applications. It can be interfaced with FPGA applications quite easily similar to interfacing an arbitrary IP core block. The proposed real-time DMM differs from other conventional memory allocators in a way that it allows for memory allocations composed of differing size blocks that are not necessarily contiguous. The address translator block in design provides to access separate non-contiguous blocks as a whole contiguous chunk of memory. Implementation and verification of the developed DMM on an FPGA demo board is also presented using synthetic memory request streams.


A Mobile Computing Framework Based on Adaptive Mobile Code Offloading
Kaya, Mahir; Koçyiğit, Altan; Eren, Pekin Erhan (2014-08-29)
Smartphones are not capable of competing against their desktop counterparts or servers in terms of CPU speed, battery, memory and storage. However, a mobile device can transparently use cloud resources by employing an offloading mechanism. Offloading enables mobile devices to run computation intensive applications such as object recognition, Optical Character Recognition (OCR) and augmented reality. In this paper, an Inversion of Control (IoC) based offloading technique is proposed in order to overcome shor...
Parallel Scalable PDE Constrained Optimization Antenna Identification in Hyperthermia Cancer Treatment Planning
SCHENK, Olaf; Manguoğlu, Murat; CHRİSTEN, Matthias; SATHE, Madan (Springer Science and Business Media LLC, 2009-01-01)
We present a PDE-constrained optimization algorithm which is designed for parallel scalability on distributed-memory architectures with thousands of cores. The method is based on a line-search interior-point algorithm for large-scale continuous optimization, it is matrix-free in that it does not require the factorization of derivative matrices. Instead, it uses a new parallel and robust iterative linear solver on distributed-memory architectures. We will show almost linear parallel scalability results for t...
An Application-aware DRAM controller
Cilasın, Ramazan; Bazlamaçcı, Cüneyt Fehmi; Department of Electrical and Electronics Engineering (2019)
Considering that emerging technologies have started to require excessive amount of memory, with quick response times and low power consumption, more efficient memory systems has become a crucial need for almost every system ranging from mobile phones to data centers. However, there exists a gap between CPU and memory speeds and most application execution times depend almost entirely on the speed at which RAM can send data to the CPU. As for the main memory, DDRx DRAM’s relatively low-latency, high density a...
Generalized resource management for heterogeneous cloud data centers
Erol, Ahmet; Güran Schmidt, Şenan Ece.; Department of Electrical and Electronics Engineering (2019)
OpenStack is a widely used management tool for cloud computing which is designed to work on servers and allocate standard computing resources such as CPU, memory or disk. The current trend for integrating different hardware accelerators such as FPGAs and GPUs in the cloud requires managing these heterogeneous resources. In this thesis, we propose a generalization for OpenStack Nova project which extends the relevant data structures to include these new resources. More importantly, we present a new lightweig...
GOKMEN, A; YALCIN, S (1992-01-01)
A versatile interface card for Apple IIe computer and various peripheral devices are designed to control instruments which generates transient signals like in graphite furnace atomic spectrometer. The interface card consists of a multiplexed analog-to-digital converter, a digital-to-analog converter, and a timer/counter chip. The timer/counter chip with 16 built-in registers can be programmed in many modes which provides a time base for real-time measurements. A stepper motor runs under the control of ti...
Citation Formats
C. Özer, “A Dynamic memory manager for FPGA applications/,” M.S. - Master of Science, Middle East Technical University, 2014.