A Dynamic memory manager for FPGA applications/

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2014
Özer, Cenk
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Recently, FPGAs are shipped with a large amount of internal memory (block RAM) sufficient to perform many complex computations without a need for off-chip memory. However, block RAMs (BRAMs) of FPGAs should be used efficiently especially for computations that need dynamic management of the memory. Thus, within the scope of this thesis work, a dynamic memory manager (DMM) unit is designed with an objective of meeting memory requests with a low fragmentation at runtime for FPGA applications. The unit is designed to have a bounded response time for dynamic memory requests to be suitable for real time applications. It can be interfaced with FPGA applications quite easily similar to interfacing an arbitrary IP core block. The proposed real-time DMM differs from other conventional memory allocators in a way that it allows for memory allocations composed of differing size blocks that are not necessarily contiguous. The address translator block in design provides to access separate non-contiguous blocks as a whole contiguous chunk of memory. Implementation and verification of the developed DMM on an FPGA demo board is also presented using synthetic memory request streams.
Memory management (Computer science)., Computer architecture., Field programmable gate arrays.
http://etd.lib.metu.edu.tr/upload/12617472/index.pdf
https://hdl.handle.net/11511/23735
Graduate School of Natural and Applied Sciences, Thesis

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Citation Formats
C. Özer, “A Dynamic memory manager for FPGA applications/,” M.S. - Master of Science, Middle East Technical University, 2014.
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