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An Application-aware DRAM controller

Cilasın, Ramazan
Considering that emerging technologies have started to require excessive amount of memory, with quick response times and low power consumption, more efficient memory systems has become a crucial need for almost every system ranging from mobile phones to data centers. However, there exists a gap between CPU and memory speeds and most application execution times depend almost entirely on the speed at which RAM can send data to the CPU. As for the main memory, DDRx DRAM’s relatively low-latency, high density and low cost made it the technology choice. DRAM market is a cost-sensitive market and architectural changes in DRAM is not easily welcomed by the manufacturers. On the other hand, DRAM is managed by Memory Controller which provides an interface between requestors and DRAM, and changes to the Memory Controller might have considerable effect on mitigating the problems incurred by slow memory. In this thesis work, DRAM Controllers for general purpose computers are focused on and based on the problem mentioned above the following algorithmic contributions and proposals are made: (i) an application aware memory scheduling algorithm to reduce the main memory interference and to provide fairness (ii) a hybrid page policy to avoid unnecessary activations, (iii) a dynamic command scheduling scheme that is essential for providing flexibility, (iv) a refresh scheduling method to decrease latency and power consumption, (v) an efficient way of using power-down modes to provide balance between latency and power consumption, (vi) integration of a memory access latency reduction method which is using the intrinsic DRAM characteristics. This thesis work’s resultant controller provides a performance benefit of 9.31% on average compared to a recently proposed application aware controller, while serving fairer to applications and consuming lower power at the expense of higher storage cost. Proposed methods are simple to implement and can be used in a modern memory controller.