Design of H.264/AVC compatible intra-frame video encoder on FPGA programmable logic devices /

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2014

Author

Günay, Ömer

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Video compression is a technique used to reduce the amount of data in a video to limit the amount of storage space and bandwidth it requires. H.264/AVC is a widely used video compression standard developed together by the ISO (International Organization for Standardization) Moving Picture Experts Group (MPEG) and the ITU (International Telecommunication Union) Video Coding Experts Group (VCEG). H.264/AVC offers an extended range of algorithms for coding digital video to achieve superior compression efficiency with respect to previous standards, which increases computational complexity of H.264/AVC encoders and decoders. In this thesis, an H.264/AVC compatible intra-frame video encoder is designed and implemented on FPGA devices. First, a reference encoder which includes encoding algorithms such as intra prediction, intra mode selection, transform, quantization and entropy coding, are implemented and tested in MATLAB environment. Then, the reference encoder is coded in VHDL language and tested using the Mentor Graphics Modelsim HDL simulation tool. Next, the overall FPGA implementation is tested by putting the H.264 coded bitstream into transport stream packets, streaming with UDP over Ethernet and decoding with VLC Player software on a PC. All video resolutions and frame rates defined in H.264 standard are supported by the implemented encoder.

Subject Keywords

Video compression., Field programmable gate arrays., Programmable logic devices., Integer transform., Coding theory.

URI

http://etd.lib.metu.edu.tr/upload/12617751/index.pdf
https://hdl.handle.net/11511/23988

Collections

Graduate School of Natural and Applied Sciences, Thesis

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Citation Formats

Ö. Günay, “Design of H.264/AVC compatible intra-frame video encoder on FPGA programmable logic devices /,” M.S. - Master of Science, Middle East Technical University, 2014.