Date

2016

Author

Baloğlu, Eyüp Can

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Surface deformations and thermal stress behavior of microelectronic devices that operate at cryogenic temperatures (less than 120 K) and under vacuum conditions are important phenomena that aff ect the reliability requirements of such components. Excessive deformation and thermal stress on these devices may result in interconnect failure, performance degradation or other direct mechanical failure of one or more components. To obtain reliable products, surface deformations, named as warpage most widely, and thermal stresses should be optimized. The sources of the warpage and thermal stresses are large di fferences between the operation and storage temperatures of such devices, and the existence of thermal mismatch caused by materials having di fferent thermal expansion coeffi cients. In this study, an experimental setup is utilized to measure out of plane surface deformations of integrated assemblies at cryogenic temperatures as well as at room temperature. The test setup is equipped with a phase shifting Fizeau laser interferometer system. To reach cryogenic temperatures liquid nitrogen is used. Four diff erent measurement error sources are de fined and contribution of each source is determined by experimental methods, analytical solutions or by using fi nite element analysis. Optical path change due to the di fference between optical window temperatures at the initial and fi nal states causes 61.3 nm di fference. Natural surface topology of optical window (BK7) changes the peak to valley (PV) di fference value of a sample by an amount of 27.2 nm. The e ffect of optical window tilt angle on PV is determined as 30 nm by testing the same sample at three diff erent optical window tilt angles. Finally the PV di fference of a sample caused by the det ection of the optical window related to pressure diff erence on top and bottom surfaces is determined as 15 nm. According to the results of a parametric fi nite element analysis on a ceramic-epoxy-silicon trimaterial assembly, a minimum warpage with a value of 0.13 u m exists for layer thicknesses of 1.27 mm ceramic, 0.075 mm epoxy and 0.1 mm silicon due to a temperature change between room temperature and 80 K whereas a maximum warpage of 20.60 um exists for layer thicknesses of 0.63 mm ceramic, 0.5 mm epoxy and 0.1 mm silicon. Moreover, it is observed that increasing the ceramic thickness or decreasing the silicon thickness by keeping other layer thicknesses constant decreases the warpage. A total number of eight samples with di fferent ceramic and silicon thicknesses are experimentally studied. In some cases, a whole fi eld fringe formation is not observed for the silicon surface because of excessive deformation of the sample. In these cases, a spherical bending is assumed and the radius of curvature value of the sample is determined at 80 K. An extrapolation of observed results is used to determine 80 K warpage value of such samples. The remaining sample results can be obtained directly from measurements. For the integrated structure that contains 0.1 mm thick silicon, successful warpage measurement could not be obtained even at room temperature due to excessive deformation of the sample. For all of the remaining seven cases, the diff erence between the fi nite element analysis and experimental results is within 12.0%. 

Subject Keywords

Cryoelectronics., Microelectronics., Superconductivity., Low temperature engineering.

URI

http://etd.lib.metu.edu.tr/upload/12620479/index.pdf 
https://hdl.handle.net/11511/25954

Collections

Graduate School of Natural and Applied Sciences, Thesis