Hardware design and implementation of packet fair queuing algorithms for the quality of service support in the high-speed internet

Date

2012-09-05

Author

Sanli, Mustafa
Schmidt, Şenan Ece
Guran, Hasan Cengiz

Metadata

Show full item record

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

Item Usage Stats

232
views

0
downloads

The increasing amount of real-time traffic carried over the Internet requires end-to-end quality of service (QoS) support. To this end, the QoS Schedulers, that are implemented in routers, assign the available bandwidth resources to packet flows according to their respective allocated rates. Packet Fair Queuing (PFQ) schedulers can provide fair service and low end-to-end delay bound to the traffic flows. However, they have higher implementation complexity compared to other algorithms, because of the requirements of tracking the system state, and searching for the packet to get service among all flows, that are queued at the outgoing interface. QoS scheduling is a data plane functionality, which requires hardware implementation for high speed router interfaces. The previous works on hardware implementation of PFQ schedulers are specific to certain algorithms, and they do not provide any results on real hardware platforms. In this paper, we present a general hardware design framework for PFQ schedulers, and apply this framework to the WF(2)Q+ PFQ algorithm to demonstrate its properties. We carry out the entire implementation of the WF(2)Q+ algorithm on an FPGA, and evaluate its performance with real traffic flows. In addition, we implement WFQ as a second PFQ algorithm to demonstrate the generality of the framework.

Subject Keywords

Quality of service, Packet fair queuing, FPGA

URI

https://hdl.handle.net/11511/38517

Journal

COMPUTER NETWORKS

DOI

https://doi.org/10.1016/j.comnet.2012.04.015

Collections

Department of Electrical and Electronics Engineering, Article

Suggestions

OpenMETU
Core

Design and implementation of scheduling and switching architectures for high speed networks Sanlı, Mustafa; Güran, Hasan Cengiz; Schmidt, Şenan Ece; Department of Electrical and Electronics Engineering (2011) Quality of Service (QoS) schedulers are one of the most important components for the end-to-end QoS support in the Internet. The focus of this thesis is the hardware design and implementation of the QoS schedulers, that is scalable for high line speeds and large number of traffic flows. FPGA is the selected hardware platform. Previous work on the hardware design and implementation of QoS schedulers are mostly algorithm specific. In this thesis, a general architecture for the design of the class of Packet Fa...
Connectionless traffic and variable packet size support in high speed network switches : improvements for the delay-limiter switch Akçasoy, Alican; Schmidt, Şenan Ece; Department of Electrical and Electronics Engineering (2008) Quality of Service (QoS) support for real-time traffic is a critical issue in high speed networks. The previously proposed Delay-Limiter Switch working with the Framed-Deadline Scheduler (FDS) is a combined input-output queuing (CIOQ) packet switch that can provide end-to-end bandwidth and delay guarantees for connection-oriented traffic. The Delay-Limiter Switch works with fixed-size packets. It has a scalable architecture and can provide QoS support for connection-oriented real-time traffic in a low-compl...
Frame-counter scheduler: A novel QoS scheduler for real-time traffic Schmidt, Şenan Ece (Elsevier BV, 2006-08-04) Real-time traffic communication has Quality of Service (QoS) requirements such as end-to-end bandwidth and delay guarantees.
A Flow Aggregation Method for the Scalable and Efficient Quality of Service Support in Next Generation Networks Sanli, Mustafa; Schmidt, Şenan Ece; Guran, Hasan Cengiz (2013-12-13) The services in the Next Generation Network (NGN) will be created on demand by the customers and will require end-to-end Quality of Service (QoS) for each flow. A very significant component for the end-to-end QoS support in the Internet is the packet schedulers in the routers. The complexity of the packet scheduling algorithms increases with the number of flows. As a solution, flow aggregation decreases the number of flows processed by the scheduler. The previous work in the literature proves that if the fl...
Switch fabric schedulers with intelligent multi-class support: design, implementation and evaluation on FPGA / Akpınar, Murat; Schmidt, Şenan Ece; Department of Electrical and Electronics Engineering (2014) The applications in the contemporary computer networks require end-to-end Quality of Service (QoS). Moreover, diff erent applications have di fferent QoS requirements. Thus, it is important to support QoS in the network layer routers which can be achieved by scheduling the output queues in output queued routers. However, pure output queued routers are not easy to build. Hence, it is important to equip the fabric schedulers of input queued switches with QoS support. Thus, it is an important research problem ...

Citation Formats

M. Sanli, Ş. E. Schmidt, and H. C. Guran, “Hardware design and implementation of packet fair queuing algorithms for the quality of service support in the high-speed internet,” COMPUTER NETWORKS, pp. 3065–3075, 2012, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/38517.