Show/Hide Menu
Hide/Show Apps
Logout
Türkçe
Türkçe
Search
Search
Login
Login
OpenMETU
OpenMETU
About
About
Open Science Policy
Open Science Policy
Open Access Guideline
Open Access Guideline
Postgraduate Thesis Guideline
Postgraduate Thesis Guideline
Communities & Collections
Communities & Collections
Help
Help
Frequently Asked Questions
Frequently Asked Questions
Guides
Guides
Thesis submission
Thesis submission
MS without thesis term project submission
MS without thesis term project submission
Publication submission with DOI
Publication submission with DOI
Publication submission
Publication submission
Supporting Information
Supporting Information
General Information
General Information
Copyright, Embargo and License
Copyright, Embargo and License
Contact us
Contact us
Switch fabric schedulers with intelligent multi-class support: design, implementation and evaluation on FPGA /
Download
index.pdf
Date
2014
Author
Akpınar, Murat
Metadata
Show full item record
Item Usage Stats
186
views
84
downloads
Cite This
The applications in the contemporary computer networks require end-to-end Quality of Service (QoS). Moreover, diff erent applications have di fferent QoS requirements. Thus, it is important to support QoS in the network layer routers which can be achieved by scheduling the output queues in output queued routers. However, pure output queued routers are not easy to build. Hence, it is important to equip the fabric schedulers of input queued switches with QoS support. Thus, it is an important research problem to support QoS in input queued routers. In this thesis we investigate the VOQ fabric scheduler algorithms. Better QoS support for di fferent applications is possible by implementing per flow queues at the input ports rather than coarse virtual output queues per output port. The first contribution of this thesis is an intelligent multi-class (IMC) VOQ architecture which is independent from fabric scheduler algorithms. Additionally, 2 di fferent algorithms are proposed for intelligent side of the IMC VOQ architecture. The second contribution is a modular hardware design for fabric schedulers that support multi class. The design is carried out on FPGA by implementing the well-known ISLIP together with the proposed IMC unit. The correctness of the operation of the designed hardware is verified by comparing to a software simulator. The thesis further presents discussions of implementing other scheduler algorithms using the same hardware architecture and its scalability. The thesis presents the evaluation of FPGA resource usage of proposed IMC VOQ iSLIP.
Subject Keywords
Computer networks.
,
End-to-end delay (Computer networks).
,
Quality of service (Computer networks).
,
Field programmable gate arrays.
URI
http://etd.lib.metu.edu.tr/upload/12617791/index.pdf
https://hdl.handle.net/11511/23993
Collections
Graduate School of Natural and Applied Sciences, Thesis
Suggestions
OpenMETU
Core
Data plane-based defense system against DDoS attacks for software defined networks
Gözütok, Ahmet; Bazlamaçcı, Cüneyt Fehmi; Department of Electrical and Electronics Engineering (2018)
Software Defined Network (SDN) is a new networking architecture. It offers promising advances and provides remarkable solutions to certain challenges in this area, yet it is still vulnerable to Distributed Denial of Service (DDoS) attacks. DDoS attacks cause devastating impacts on the SDN architecture, which may lead to failure of an entire SDN network. There is no generally accepted network defense system against these attacks for SDN architecture; in addition, there are many unresolved problems in this ar...
UNIBUS: a universal hardware architecture for serial bus interfaces with real-time support /
Duman, Mehdi; Schmidt, Şenan Ece; Department of Electrical and Electronics Engineering (2015)
Serial bus communication is widely used in different application areas such as Ethernet in computer networking, CAN bus in in-vehicle communications, MIL-STD 1553B in military avionics and UART for peripheral device communication. This thesis work presents UNIBUS (Universal Bus); an abstract, generic block level hardware architecture for implementing serial bus interfaces. UNIBUS realizes the physical and data link layer functions supporting the strict timing requirements for bit operations and synchronizat...
Tool support for worst case end to end delay analysis of AFDX networks
Efe, Orhun; Bazlamaçcı, Cüneyt Fehmi; Department of Electrical and Electronics Engineering (2016)
Avionics Full Duplex Switched Ethernet (AFDX) is among the major technological components used in avionics systems. Since its publication, AFDX has spread out rapidly and has been deployed in major aircrafts such as Airbus A400M, Boeing 787, Bombardier C Series, etc. In AFDX networks, data is exchanged between end systems by utilizing tunnels. For certification purposes, finding a safe upper bound is required in transmission process. UPPAAL is already shown to be useful for performing such a delay analysis ...
Frame-counter scheduler: A novel QoS scheduler for real-time traffic
Schmidt, Şenan Ece (Elsevier BV, 2006-08-04)
Real-time traffic communication has Quality of Service (QoS) requirements such as end-to-end bandwidth and delay guarantees.
Improving performance of network intrusion detection systems through concurrent mechanisms
Atakan, Mustafa; Şener, Cevat; Department of Computer Engineering (2003)
As the bandwidth of present networks gets larger than the past, the demand of Network Intrusion Detection Systems (NIDS) that function in real time becomes the major requirement for high-speed networks. If these systems are not fast enough to process all network traffic passing, some malicious security violations may take role using this drawback. In order to make that kind of applications schedulable, some concurrency mechanism is introduced to the general flowchart of their algorithm. The principal aim is...
Citation Formats
IEEE
ACM
APA
CHICAGO
MLA
BibTeX
M. Akpınar, “Switch fabric schedulers with intelligent multi-class support: design, implementation and evaluation on FPGA /,” M.S. - Master of Science, Middle East Technical University, 2014.