Scalable high-performance architecture for convolutional ternary neural networks on FPGA

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2017-09-06

Author

Prost-Boucle, Adrien
Bourge, Alban
Petrot, Frederic
Alemdar, Hande
Caldwell, Nicholas
Leroy, Vincent

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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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Thanks to their excellent performances on typical artificial intelligence problems, deep neural networks have drawn a lot of interest lately. However, this comes at the cost of large computational needs and high power consumption. Benefiting from high precision at acceptable hardware cost on these difficult problems is a challenge. To address it, we advocate the use of ternary neural networks (TNN) that, when properly trained, can reach results close to the state of the art using floating-point arithmetic. We present a highly versatile FPGA friendly architecture for TNN in which we can vary both the number of bits of the input data and the level of parallelism at synthesis time, allowing to trade throughput for hardware resources and power consumption. To demonstrate the efficiency of our proposal, we implement high-complexity convolutional neural networks on the Xilinx Virtex-7 VC709 FPGA board. While reaching a better accuracy than comparable designs, we can target either high throughput or low power. We measure a throughput up to 27000 fps at approximate to 7 W or up to 8.36 TMAC/s at approximate to 13 W.

Subject Keywords

Neurons, Parallel processing, Random access memory, Field programmable gate arrays, Hardware, Throughput, Neural networks

URI

https://hdl.handle.net/11511/41133

DOI

https://doi.org/10.23919/fpl.2017.8056850

Collections

Department of Computer Engineering, Conference / Seminar

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Citation Formats

A. Prost-Boucle, A. Bourge, F. Petrot, H. Alemdar, N. Caldwell, and V. Leroy, “Scalable high-performance architecture for convolutional ternary neural networks on FPGA,” 2017, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/41133.