Show/Hide Menu
Hide/Show Apps
Logout
Türkçe
Türkçe
Search
Search
Login
Login
OpenMETU
OpenMETU
About
About
Open Science Policy
Open Science Policy
Open Access Guideline
Open Access Guideline
Postgraduate Thesis Guideline
Postgraduate Thesis Guideline
Communities & Collections
Communities & Collections
Help
Help
Frequently Asked Questions
Frequently Asked Questions
Guides
Guides
Thesis submission
Thesis submission
MS without thesis term project submission
MS without thesis term project submission
Publication submission with DOI
Publication submission with DOI
Publication submission
Publication submission
Supporting Information
Supporting Information
General Information
General Information
Copyright, Embargo and License
Copyright, Embargo and License
Contact us
Contact us
Boostıng performance of hls optımızatıon for soc based hardware accelerators.
Download
index.pdf
Date
2020
Author
Kocaay, Aziz Berkin
Metadata
Show full item record
This work is licensed under a
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License
.
Item Usage Stats
279
views
158
downloads
Cite This
Modern large-scale computing algorithms require huge amount of computational power. In adapting to increasing computation demands, FPGA-based SoC platforms provide an alternative to traditional CPU or GPU units, which suffer from thermal problems, power issues, etc. However, design flow for FPGA based development may be hard and time-consuming for an average software engineer who has limited knowledge about hardware design. A new approach in FPGA-based system development without the need for a hardware engineer is to program the FPGA using high level synthesis (HLS) tools that resembles C-based languages. Commercial HLS tools provide different kinds of automatic and user-defined optimizations for loop kernels such as pipelining, loop unrolling, etc. However, these techniques only provide instruction-level pipelining and reduce loop enter and exit overheads to decrease execution time of algorithms running on programmable logic (PL) side of SoC systems. The limited approach of HLS for loop kernels can be extended by adding front-end operations to input code of HLS tools. In this thesis, we propose a semi-autonomous polyhedral analysis and optimization-based methodology in order to enable course grained parallelization on nested loop structures to increase final design efficiency. Xilinx Zynq SoC FPGA platform and Vivado Design Suite Tool are used in order to show how our proposed approach could be applied.
Subject Keywords
Parallel processing (Electronic computers).
,
Keywords: Polyhedral Modelling
,
Hardware Accelerator
,
System on Chip (SoC)
,
High Level Synthesis
,
Parallel Processing
,
Zynq.
URI
http://etd.lib.metu.edu.tr/upload/12625230/index.pdf
https://hdl.handle.net/11511/45480
Collections
Graduate School of Natural and Applied Sciences, Thesis
Suggestions
OpenMETU
Core
Data-parallel programming on Helios, Parallel environment and PVM
Sener, C; Paker, Y; Kiper, A (1996-09-27)
Parallel computing, increasingly used for computationally intensive problems, requires considerable expertise and time, limiting then widespread use. This article presents a data-parallel programming tool to simplify the task of developing parallel programs based on data-parallel type. It has been originally developed for the Hellos operating system running on a network of Transputers, and then ported to the IBM SP/2 system executing two parallel programming environments. With its interface to the C languag...
Optimization of XNOR Convolution for Binary Convolutional Neural Networks on GPU
Kaya, Mete Can; İnci, Alperen; Temizel, Alptekin (2020-10-09)
Binary convolutional networks have lower computational load and lower memory foot-print compared to their full-precision counterparts. So, they are a feasible alternative for the deployment of computer vision applications on limited capacity embedded devices. Once trained on less resourceconstrained computational environments, they can be deployed for real-time inference on such devices. In this study, we propose an implementation of binary convolutional network inference on GPU by focusing on optimization ...
Cell-vertex based parallel and adaptive explicit 3D flow solution on unstructured grids
Yilmaz, E; Kavsaoglu, MS; Akay, HU; Akmandor, IS (Informa UK Limited, 2001-01-01)
A parallel adaptive Euler flow solution algorithm is developed for 3D applications on distributed memory computers. Significant contribution of this research is the development and implementation of a parallel grid adaptation scheme together with an explicit cell vertex-based finite volume 3D flow solver on unstructured tetrahedral grids. Parallel adaptation of grids is based on grid-regeneration philosophy by using an existing serial grid generation program. Then, a general partitioner repartitions the gri...
Case studies on the use of neural networks in eutrophication modeling
Karul, C; Soyupak, S; Cilesiz, AF; Akbay, N; Germen, E (2000-10-30)
Artificial neural networks are becoming more and more common to be used in development of prediction models for complex systems as the theory behind them develops and the processing power of computers increase. A three layer Levenberg-Marquardt feedforward learning algorithm was used to model the eutrophication process in three water bodies of Turkey (Keban Dam Reservoir, Mogan and Eymir Lakes). Despite the very complex and peculiar nature of Keban Dam, a relatively good correlation (correlation coefficient...
A new approach to mathematical water quality modeling in reservoirs: Neural networks
Karul, C; Soyupak, S; Germen, E (1998-01-01)
Neural Networks are becoming more and more valuable tools for system modeling and function approximation as computing power of microcomputers increase. Modeling of complex ecological systems such as reservoir limnology is very difficult since the ecological interactions within a reservoir are difficult to define mathematically and are usually system specific. To illustrate the potential use of Neural Networks in ecological modeling, a software was developed to train the data from Keban Dam Reservoir by back...
Citation Formats
IEEE
ACM
APA
CHICAGO
MLA
BibTeX
A. B. Kocaay, “Boostıng performance of hls optımızatıon for soc based hardware accelerators.,” Thesis (M.S.) -- Graduate School of Natural and Applied Sciences. Electrical and Electronics Engineering., Middle East Technical University, 2020.