A CAD environnnent for digital filters using a VerilogHDL based functional bit-serial compiler

This paper reports the development of a highly integrated CAD environment for area efficient implementation of digital filters using commercially available CAD tools. The environment establishes a plain interface between CADENCE (an IC design framework), MATLAB (a mathematical computation tool), and BITMAP (a new custom-developed filter compiler). The new compiler allows the functional description of the target filter in the Verilog hardware description language (VerilogHDL), generating technology independent and retargetable digital filters in the bit-serial architecture. This integrated design environment shortens the implementation time, reduces the number of gates, and minimizes the overall filter area. The CAD environment and the new functional compiler have been used to implement a mixed-signal ASIC chip with thirteen digital IIR and FIR filters, three pairs of over sampled A/D and D/A converters, parallel port and I/sup 2/C type microprocessor interfaces, and a number of analog interface circuits. The chip occupies an 81 mm/sup 2/ area in a 0.7 /spl mu/m CMOS technology.


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Citation Formats
T. Akın, “A CAD environnnent for digital filters using a VerilogHDL based functional bit-serial compiler,” 1998, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/41322.