Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs

Date

2011-09-14

Author

Erdem, Oguzhan
Le, Hoang
Prasanna, Viktor K.
Bazlamaçcı, Cüneyt Fehmi

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This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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Network router virtualization has recently gained much interest in the research community, as it allows multiple virtual router instances to run on a common physical router platform. The key metrics in designing network virtual routers are (1) number of supported virtual router instances, (2) total number of prefixes, and (3) ability to quickly update the virtual table. Existing merging algorithms use leaf pushing and a shared next hop data structure to eliminate the large memory bandwidth requirement. However, the size of the shared next hop table grows linearly with the number of virtual routers. Due to the limited amount of on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), existing designs cannot support large number of tables and/or large number of prefixes.

Subject Keywords

IP networks, Data structures, Routing, Pipeline processing, Memory management, Field programmable gate arrays, Redundancy

URI

https://hdl.handle.net/11511/52860

Conference Name

22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

Collections

Department of Electrical and Electronics Engineering, Conference / Seminar

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Citation Formats

O. Erdem, H. Le, V. K. Prasanna, and C. F. Bazlamaçcı, “Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs,” presented at the 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Santa Monica, CA, 2011, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/52860.