Show/Hide Menu
Hide/Show Apps
Logout
Türkçe
Türkçe
Search
Search
Login
Login
OpenMETU
OpenMETU
About
About
Open Science Policy
Open Science Policy
Open Access Guideline
Open Access Guideline
Postgraduate Thesis Guideline
Postgraduate Thesis Guideline
Communities & Collections
Communities & Collections
Help
Help
Frequently Asked Questions
Frequently Asked Questions
Guides
Guides
Thesis submission
Thesis submission
MS without thesis term project submission
MS without thesis term project submission
Publication submission with DOI
Publication submission with DOI
Publication submission
Publication submission
Supporting Information
Supporting Information
General Information
General Information
Copyright, Embargo and License
Copyright, Embargo and License
Contact us
Contact us
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
Date
2008-02-22
Author
Ismailoglu, A. Neslin
Askar, Murat
Metadata
Show full item record
This work is licensed under a
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License
.
Item Usage Stats
208
views
0
downloads
Cite This
A delay-insensitivity verification method is proposed for bit-level pipelined systolic dual-rail threshold logic adders, which achieve speed-up through early and input-incomplete carry output generation and which employ bit-wise completion at pipeline registers. The proposed method simplifies the verification task significantly, regardless of the operand length of the adder, such that analysis of three adjacent systoles for the eight possible early/late carry output generation scenarios is sufficient for detecting the input combinations which violate delay insensitivity. Using this method, structural modifications for re-establishing delay-insensitivity could be devised without sacrificing the speed-up advantages due to early carry generation. The method could also be applied to other pipelined data processing applications in dual-rail threshold logic.
Subject Keywords
Asynchronous logic circuits
,
Systolic arrays
,
Pipeline processing
,
Pipeline arithmetic
URI
https://hdl.handle.net/11511/64479
Conference Name
7th WSEAS International Conference on Electronics , Hardware, Wireless and Optical Communications
Collections
Department of Electrical and Electronics Engineering, Conference / Seminar
Suggestions
OpenMETU
Core
Wave component sampling method for high performance pipelined circuits
Sever, Refik; Aşkar, Murat; Department of Electrical and Electronics Engineering (2011)
In all of the previous pipelining methods such as conventional pipelining, wave pipelining, and mesochronous pipelining, a data wave propagating on the combinational circuit is sampled whenever it arrives to a synchronization stage. In this study, a new wave-pipelining methodology named as Wave Component Sampling Method (WCSM), is proposed. In this method, only the component of a wave, whose maximum and minimum delay difference exceeds the tolerable value, is sampled, and the other components continue to pr...
Application of bit-level pipelining to delay insensitive null convention adders
Ismailoglu, A. Neslin; Askar, Murat (2007-05-30)
In this study, two asynchronous delay insensitive adder topologies in Null Convention Logic [1] style are adopted for bit-level pipelining: The reduced Null Convention Logic Adder [2] and a Null Convention Carry Save Adder. When pipelined at bit-level, early carry generation feature of both adders violate the requirements of delay insensitivity. To solve this problem, new topologies are proposed. Resultant adders maintain both reliable delay insensitive operation and speedup advantages of early carry genera...
Numerical implementation of magneto-acousto-electrical tomography (MAET) using a linear phased array transducer
GÖZÜ, Mehmet Soner; ZENGİN, Reyhan; Gençer, Nevzat Güneri (2018-02-01)
In this study, the performance and implementation of magneto-acousto-electrical tomography (MAET) is investigated using a linear phased array (LPA) transducer. The goal of MAET is to image the conductivity distribution in biological bodies. It uses the interaction between ultrasound and a static magnetic field to generate velocity current density distribution inside the body. The resultant voltage due to velocity current density is sensed by surface electrodes attached on the body. In this study, the theory...
Concurrency control in distributed databases through time intervals and short-term locks
Halıcı, Uğur (Institute of Electrical and Electronics Engineers (IEEE), 1989)
A method for concurrency control in distributed database management systems that increases the level of concurrent execution of transactions, called ordering by serialization numbers (OSN), is proposed. The OSN method works in the certifier model and uses time-interval techniques in conjunction with short-term locks to provide serializability and prevent deadlocks. The scheduler is distributed, and the standard transaction execution policy is assumed, that is, the read and write operations are issued contin...
Stabilization of the Fast Multipole Method for Low Frequencies Using Multiple-Precision Arithmetic
Karaosmanoglu, Bariscan; Ergül, Özgür Salih (2014-08-23)
We stabilize a conventional implementation of the fast multipole method (FMM) for low frequencies using multiple-precision arithmetic (MPA). We show that using MPA is a direct remedy for low-frequency breakdowns of the standard diagonalization, which is prone to numerical errors at short distances with respect to wavelength. By increasing the precision, rounding errors are suppressed until a desired level of accuracy is obtained with plane-wave expansions. As opposed to other approaches in the literature, u...
Citation Formats
IEEE
ACM
APA
CHICAGO
MLA
BibTeX
A. N. Ismailoglu and M. Askar, “Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders,” Univ Cambridge, Cambridge, ENGLAND, 2008, p. 23, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/64479.