Show/Hide Menu
Hide/Show Apps
Logout
Türkçe
Türkçe
Search
Search
Login
Login
OpenMETU
OpenMETU
About
About
Open Science Policy
Open Science Policy
Open Access Guideline
Open Access Guideline
Postgraduate Thesis Guideline
Postgraduate Thesis Guideline
Communities & Collections
Communities & Collections
Help
Help
Frequently Asked Questions
Frequently Asked Questions
Guides
Guides
Thesis submission
Thesis submission
MS without thesis term project submission
MS without thesis term project submission
Publication submission with DOI
Publication submission with DOI
Publication submission
Publication submission
Supporting Information
Supporting Information
General Information
General Information
Copyright, Embargo and License
Copyright, Embargo and License
Contact us
Contact us
Application of bit-level pipelining to delay insensitive null convention adders
Date
2007-05-30
Author
Ismailoglu, A. Neslin
Askar, Murat
Metadata
Show full item record
This work is licensed under a
Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License
.
Item Usage Stats
149
views
0
downloads
Cite This
In this study, two asynchronous delay insensitive adder topologies in Null Convention Logic [1] style are adopted for bit-level pipelining: The reduced Null Convention Logic Adder [2] and a Null Convention Carry Save Adder. When pipelined at bit-level, early carry generation feature of both adders violate the requirements of delay insensitivity. To solve this problem, new topologies are proposed. Resultant adders maintain both reliable delay insensitive operation and speedup advantages of early carry generation, with O(log n) average completion time for n-bit addition and -as a result of bit-level pipelining- constant throughput against increased bit-length.
Subject Keywords
IEEE International Symposium on Circuits and Systems
,
Pipeline processing
,
Delay
,
Circuits
,
Adders
,
Maintenance
,
Throughput
,
Logic
,
Clocks
,
Registers
,
Hysteresis
URI
https://hdl.handle.net/11511/65279
DOI
https://doi.org/10.1109/iscas.2007.378167
Collections
Department of Electrical and Electronics Engineering, Conference / Seminar
Suggestions
OpenMETU
Core
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
Ismailoglu, A. Neslin; Askar, Murat (2008-02-22)
A delay-insensitivity verification method is proposed for bit-level pipelined systolic dual-rail threshold logic adders, which achieve speed-up through early and input-incomplete carry output generation and which employ bit-wise completion at pipeline registers. The proposed method simplifies the verification task significantly, regardless of the operand length of the adder, such that analysis of three adjacent systoles for the eight possible early/late carry output generation scenarios is sufficient for de...
ON OPERATORS OF STRONG TYPE B
Alpay, Safak (2012-10-01)
We discuss operators of strong type B between a Banach lattice and a Banach space and give necessary and sufficient conditions for this class of operators to coincide with weakly compact operators.
How to model mutually exclusive events based on independent causal pathways in Bayesian network models
Fenton, Norman; Neil, Martin; Lagnado, David; Marsh, William; Yet, Barbaros; Constantinou, Anthony (2016-12-01)
We show that existing Bayesian network (BN) modelling techniques cannot capture the correct intuitive reasoning in the important case when a set of mutually exclusive events need to be modelled as separate nodes instead of states of a single node. A previously proposed 'solution', which introduces a simple constraint node that enforces mutual exclusivity, fails to preserve the prior probabilities of the events, while other proposed solutions involve major changes to the original model. We provide a novel an...
Exit probabilities of markov modulated constrained random walks
Başoğlu Kabran, Fatma; Sezer, Ali Devin; Department of Financial Mathematics (2018)
Let X be the constrained random walk on Z2+ with increments (0, 0), (1, 0), (−1, 1), (0, −1) whose jump probabilities are determined by the state of a finite state Markov chain M. X represents the lengths of two queues of customers (or packets, tasks, etc.) waiting for service from two servers working in tandem; the arrival of customers occur with rate λ(Mk), service takes place at rates μ1(Mk), and μ2(Mk) where Mk denotes the current state of the Markov chain M. We assume that the average arrival rate is l...
Approximation of excessive backlog probabilities of two parallel queues
Ünlü, Kamil Demirberk; Sezer, Ali Devin (2018-07-25)
Let X be the constrained random walk on Z 2 + with increments (1, 0), (−1, 0), (0, 1) and (0, −1) representing the lengths at service completion times of two queues with exponentially distributed interarrival and service times running in parallel. Denote the arrival and service rates by λ i , µ i , i = 1, 2; we assume λ i < µ i , i = 1, 2, i.e., X is assumed stable. Without loss of generality we assume ρ 1 ≥ ρ 2. Let τ n be the first time X hits the line ∂A n = {x ∈ Z 2 : x(1)+x(2) = n}, i.e., when the sum ...
Citation Formats
IEEE
ACM
APA
CHICAGO
MLA
BibTeX
A. N. Ismailoglu and M. Askar, “Application of bit-level pipelining to delay insensitive null convention adders,” New Orleans, LA, 2007, p. 3259, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/65279.