Application of bit-level pipelining to delay insensitive null convention adders

Date

2007-05-30

Author

Ismailoglu, A. Neslin
Askar, Murat

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In this study, two asynchronous delay insensitive adder topologies in Null Convention Logic [1] style are adopted for bit-level pipelining: The reduced Null Convention Logic Adder [2] and a Null Convention Carry Save Adder. When pipelined at bit-level, early carry generation feature of both adders violate the requirements of delay insensitivity. To solve this problem, new topologies are proposed. Resultant adders maintain both reliable delay insensitive operation and speedup advantages of early carry generation, with O(log n) average completion time for n-bit addition and -as a result of bit-level pipelining- constant throughput against increased bit-length.

Subject Keywords

IEEE International Symposium on Circuits and Systems, Pipeline processing, Delay, Circuits, Adders, Maintenance, Throughput, Logic, Clocks, Registers, Hysteresis

URI

https://hdl.handle.net/11511/65279

DOI

https://doi.org/10.1109/iscas.2007.378167

Collections

Department of Electrical and Electronics Engineering, Conference / Seminar

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Citation Formats

A. N. Ismailoglu and M. Askar, “Application of bit-level pipelining to delay insensitive null convention adders,” New Orleans, LA, 2007, p. 3259, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/65279.