Cmos LNA design for system-on-chip receiver stages

Date

2004-09-10

Author

Telli, A
Askar, M

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In this study, narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for "System-on-Chip" receiver stages have been designed, simulated and compared using Mietec CMOS 0.7 mu m process and the Cadence/BSIM3v3 tool with active or L-biased DC-bias circuitries. Since there is an intension to use LNAs for GSM and S-band low earth orbit (LEO) space applications, the operating frequencies have been chosen as 900MHz, 2025 MHz and 2210 MHz.

Subject Keywords

low noise amplifier, LNA, Receiver

URI

https://hdl.handle.net/11511/66030

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Unclassified, Conference / Seminar

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Citation Formats

A. Telli and M. Askar, “Cmos LNA design for system-on-chip receiver stages,” 2004, p. 171, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/66030.