CMOS planar spiral inductor modeling and low noise amplifier design

Date

2006-01-01

Author

Telli, A
Demir, S
Askar, M

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During this study, various narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for GSM and S-band low earth orbit (LEO) space applications have been designed, simulated and compared using Mietec CMOS 0.7 mu m process and the Cadence/BSIM3v3. To get more realistic results, parasitic effects due to layout have been calculated and added to the simulations. Also, considering the inductive source degenerative topology, most of the attention is given on the modeling of planar spiral inductor by lumped element circuits. Moreover to decrease the substrate effects, the inductors have been surrounded by grounded guard rings and have patterned ground shield (PGS) under them. The simulation results of LNA including the parasitic effects indicate a forward gain of 9 dB with noise figure of 4.5 dB while drawing 18 mW from + 3 V supply at 22 10 MHz. The area occupied is 1.8 mm X 1.6 mm with pads, 1.3 mm X 1.2 mm without pads.

Subject Keywords

General Engineering

URI

https://hdl.handle.net/11511/66972

Journal

MICROELECTRONICS JOURNAL

DOI

https://doi.org/10.1016/j.mejo.2005.06.019

Collections

Department of Electrical and Electronics Engineering, Article

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Citation Formats

A. Telli, S. Demir, and M. Askar, “CMOS planar spiral inductor modeling and low noise amplifier design,” MICROELECTRONICS JOURNAL, pp. 71–78, 2006, Accessed: 00, 2020. [Online]. Available: https://hdl.handle.net/11511/66972.